implemented more debug features during boot

ezynq_feature_config.py

@@ -29,8 +29,8 @@ class EzynqFeatures:
             'ERR_NOT_A_FLOAT':     'Value is not a float',
             'ERR_NOT_A_BOOLEAN':   'Value is not a boolean'
             }
-    BOOLEANS=(('0','FALSE','DISABLE','DISABLED','N'),
-              ('1','TRUE', 'ENABLE','ENABLED','Y'))
+    BOOLEANS=(('0','FALSE','DISABLE','DISABLED','N','OFF'),
+              ('1','TRUE', 'ENABLE','ENABLED','Y','ON'))
 #  defines - a list, order determines HTML output order
 #  Each element has fields:
 #  'NAME' - unique name to access this parameter
@@ -146,6 +146,7 @@ class EzynqFeatures:
                     all_set=False
                     print "Configuration file is missing mandatory parameter "+self.defs[name]['CONF_NAME']+': '+self.defs[name]['DESCRIPTION']
                 else:
+                    if not self.defs[name]['DEFAULT'] is None:
                     # use default parameter
 #                    print 'Adding default : ',name,'=', self.defs[name]['DEFAULT']
                         self.pars[name]=self.defs[name]['DEFAULT']
@@ -174,6 +175,16 @@ class EzynqFeatures:
         except:
             raise Exception (name+' not found in self.defs') # should not happen with wrong data, program bug
 
+    def get_par_value_or_none(self,name):
+        try:
+            return self.pars[name]
+        except:
+            try: 
+                _=self.defs[name]['CONF_NAME']
+            except:    
+                raise Exception (name+' not found in self.defs') # should not happen with wrong data, program bug
+            return 
+
     def get_par_value(self,name):
         try:
             return self.pars[name]
@@ -222,6 +233,10 @@ class EzynqFeatures:
     def is_specified(self,name): # directly specified
         return name in self.defined
 
+    def undefine_parameter(self,name):
+        if name in self.pars:
+            self.pars[name]=None
+
     
     def set_calculated_value(self,name,value,force=True):
         if (not force) and (name in self.defined):
@@ -255,6 +270,9 @@ class EzynqFeatures:
 #            name=    self.config_names[conf_name]
             feature= self.defs[name]
             value=   self.get_par_value(name)
+            if value is None:
+                value='None'
+            else:    
                 if isinstance(value,int):
                     if (feature['TYPE']=='H'):
                         value=hex(value)

ezynq_mio.py

@@ -299,6 +299,16 @@ class EzynqMIO:
                                                      ('tri_enable',      1))) # ,force,warn)
         return led_register_set.get_register_sets(sort_addr=True,apply_new=True)
 
+    def rbl_led_on_off(self, mio_pin, led_on, reg_sets):
+        # generate code to be included in RBL register setup
+        if led_on:
+            led_on=1
+        led_register_set=  ezynq_registers.EzynqRegisters(self.MIO_PINS_DEFS,0,reg_sets)
+        led_register_set.set_bitfields('mio_pin_%02i'%mio_pin, ( # output 0 - LED off
+                                                     ('pullup',          1-led_on),
+                                                     ('tri_enable',      1-led_on))) # ,force,warn)
+        return led_register_set.get_register_sets(sort_addr=True,apply_new=True)
+
     def parse_config_mio(self,raw_configs):
         attrib_suffix='ATTRIB'
         options = {}

ezynq_uart.py

@@ -45,12 +45,12 @@ class EzynqUART:
             self.channel=None
             return
         self.channel=max(uarts)
-        self.features=ezynq_feature_config.EzynqFeatures(self.UART_CFG_DEFS,self.channel) #DDR_CFG_DEFS
+        self.features=ezynq_feature_config.EzynqFeatures(self.UART_CFG_DEFS,self.channel)
         self.features.parse_features(raw_configs)
         if len(uarts)>1:
             if 'DEBUG_CHANNEL' in self.features.pars:
                 self.channel=self.features.pars['DEBUG_CHANNEL']
-                self.features=ezynq_feature_config.EzynqFeatures(self.UART_CFG_DEFS,self.channel) #DDR_CFG_DEFS
+                self.features=ezynq_feature_config.EzynqFeatures(self.UART_CFG_DEFS,self.channel)
                 self.features.parse_features(raw_configs)
         self.uart_register_set=  ezynq_registers.EzynqRegisters(self.UART_DEFS,self.channel,[],permit_undefined_bits)
         self.slcr_register_set=  ezynq_registers.EzynqRegisters(self.SLCR_CLK_DEFS,0,[],permit_undefined_bits)
@@ -98,7 +98,23 @@ class EzynqUART:
         self.bdiv,self.cd,self.baud_rate=get_bdiv_cd_baud(self.baud_rate,min_bdiv)
         self.features.set_calculated_value('BAUD_RATE',self.baud_rate,force=True)
         
-
+    # these instructions will be usen to generate C code.
+    # when defined here (as register writes/tests) they will appear in the overall list
+    # of registers (HTML file)
+    
+    def set_uart_codes(self):
+        uart_extra_set=  ezynq_registers.EzynqRegisters(self.UART_DEFS,self.channel,[])
+        # wait transmitter FIFO empty (use before proceeding to risky of reboot code )
+        uart_extra_set.wait_reg_field_values('channel_sts',  # Channel status
+                                               (('tempty',    1)), True) # Transmitter FIFO empty (continuous)
+        uart_extra_set.flush() # to separate codes, not to combine in one write
+        # wait transmitter FIFO not full (OK to  put more characters)
+        uart_extra_set.wait_reg_field_values('channel_sts',  # Channel status
+                                               (('tful',    0)), True) # Transmitter FIFO full (continuous)
+        uart_extra_set.flush()
+        uart_extra_set.set_bitfields('tx_rx_fifo',( # TX/RX FIFO character data write/read
+                                                ('fifo',  self.cd)),True) # read/write FIFO character data
+        return uart_extra_set.get_register_sets(sort_addr=True,apply_new=True)
 
     def setup_uart(self,current_reg_sets,force=False,warn=False):    
         
@@ -157,89 +173,3 @@ class EzynqUART:
                                                 ('rxres',    0)), True, warn)
         return uart_register_set.get_register_sets(sort_addr=True,apply_new=True)
     
-#         
-# 
-#       'channel_sts':              {'OFFS': 0x02c,'DFLT':0x0,'RW':'R',
-#                                    'COMMENTS':'Channel status',
-#                                    'FIELDS':{
-#                   'reserved1':              {'r':(15,31),'d':0,'m':'R'},
-#                   'tnful':                  {'r':(14,14),'d':0,'m':'R',  'c':'Transmitter FIFO nearly full'},
-#                   'ttrig':                  {'r':(13,13),'d':0,'m':'R',  'c':'Transmitter FIFO level >= preset TTRIG value'},
-#                   'fdelt':                  {'r':(12,12),'d':0,'m':'R',  'c':'Receiver FIFO level >= preset FDEL value'},
-#                   'tactive':                {'r':(11,11),'d':0,'m':'R',  'c':'Transmitter active'},
-#                   'ractive':                {'r':(10,10),'d':0,'m':'R',  'c':'Receiver active'},
-#                   'reserved2':              {'r':( 9, 9),'d':0,'m':'R',  'c':''},
-#                   'reserved3':              {'r':( 8, 8),'d':0,'m':'R',  'c':''},
-#                   'reserved4':              {'r':( 7, 7),'d':0,'m':'R',  'c':''},
-#                   'reserved5':              {'r':( 6, 6),'d':0,'m':'R',  'c':''},
-#                   'reserved6':              {'r':( 5, 5),'d':0,'m':'R',  'c':''},
-#                   'tful':                   {'r':( 4, 4),'d':0,'m':'R',  'c':'Transmitter FIFO full (continuous)'},
-#                   'tempty':                 {'r':( 3, 3),'d':0,'m':'R',  'c':'Transmitter FIFO empty (continuous)'},
-#                   'rful':                   {'r':( 2, 2),'d':0,'m':'R',  'c':'Receiver FIFO full (continuous)'},
-#                   'rempty':                 {'r':( 1, 1),'d':0,'m':'R',  'c':'Receiver FIFO empty (continuous)'},
-#                   'rtrig':                  {'r':( 0, 0),'d':0,'m':'R',  'c':'Receiver FIFO level >= preset RTRIG value (continuous)'}}},
-           
-#        'uart_rst_ctrl':            {'OFFS': 0x228,'DFLT':0,'RW':'RW', # Never set
-#                                    'COMMENTS':'UART software reset control for reference clock and CPU_1x (AMBA) clock domains',
-#                                    'FIELDS':{
-#                   'reserved':                 {'r':( 4,31),'d':0, 'c':'reserved'},
-#                   'uart1_ref_rst':            {'r':( 3, 3),'d':0, 'c':'UART 1 reference clock domain reset: 0 - normal, 1 - reset'},
-#                   'uart0_ref_rst':            {'r':( 2, 2),'d':0, 'c':'UART 0 reference clock domain reset: 0 - normal, 1 - reset'},
-#                   'uart1_cpu1x_rst':          {'r':( 1, 1),'d':0, 'c':'UART 1 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset'},
-#                   'uart0_cpu1x_rst':          {'r':( 0, 0),'d':0, 'c':'UART 0 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset'}}},
-
- 
-#MIN_SAMPLES_PER_BIT
-
-#         clk_register_set.wait_reg_field_values('pll_status',tuple(bits), True, warn)
-# 
-#         if 'DDR' in self.pll_fdivs:
-#             clk_register_set.set_bitfields('ddr_pll_ctrl',(('pll_bypass_force',  0),
-#                                                            ('pll_bypass_qual',   0)),force,warn)
-
-
-
-
-#     writel(0x0000000f, &slcr_base->uart_rst_ctrl); /* UART reset on */
-# 
-# //&slcr_base->uart_rst_ctrl
-# //    writel(0x0000000f, &slcr_base->uart_rst_ctrl); /* UART reset on */
-#     /* delay ??? move reset on earlier?*/
-#     writel(0x00000000, &slcr_base->uart_rst_ctrl); /* UART reset off */
-# 
-# /* uart 1 */
-#     writel(0x00000020, &uart1_base->mode);     /* UART character frame */
-# /* a. Disable the Rx path: set uart.Control_reg0 [RXEN] = 0 and [RXDIS] = 1.
-#    b. Disable the Txpath: set uart.Control_reg0 [TXEN] = 0 and [TXDIS] = 1. */
-#     writel(0x00000028, &uart1_base->control); /*a,b */
-
-# /* c. Write the calculated CD value into the uart.Baud_rate_gen_reg0 [CD] bit field. */
-#     writel(12, &uart1_base->baud_rate_gen); /*c  - for 25MHz and 115200 CD=12, (BDIV+1)=18 */
-# /* d. Write the calculated BDIV value into the uart.Baud_rate_divider_reg0 [BDIV] bit value. */
-
-#     writel(17, &uart1_base->baud_rate_div); /*d  - for 25MHz and 115200 CD=12, (BDIV+1)=18 */
-#     writel(0x117, &uart1_base->control); /* restart and enable ug585v1.6.1. p 555 */
-#     writel(0x14, &uart1_base->control); /*just a delay - 1-st character is usually lost */
-
-
-
-
-
-#     def ddr_dci_calibrate(self,current_reg_sets,force=False,warn=False):
-#         ddriob_register_set=self.ddriob_register_set
-#         ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
-#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)        
-#         ddriob_register_set.flush() # close previous register settings
-#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)        
-#         ddriob_register_set.flush()# close previous register settings
-#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
-#                                                               ('enable',1),
-#                                                               ('nref_opt1',0),
-#                                                               ('nref_opt2',0),
-#                                                               ('nref_opt4',1),
-#                                                               ('pref_opt2',0),
-#                                                               ('update_control',0)),force,warn)
-# # add wait for DCI calibration DONE
-#         ddriob_register_set.wait_reg_field_values('ddriob_dci_status',('done',1), True, warn)
-# 
-#         return ddriob_register_set.get_register_sets(True,True) # close previous register settings, return new result        

ezynq_uart_defs.py

@@ -132,6 +132,12 @@ UART_DEFS={ #not all fields are defined currently
                   'rempty':                 {'r':( 1, 1),'d':0,'m':'R',  'c':'Receiver FIFO empty (continuous)'},
                   'rtrig':                  {'r':( 0, 0),'d':0,'m':'R',  'c':'Receiver FIFO level >= preset RTRIG value (continuous)'}}},
 
+      'tx_rx_fifo':            {'OFFS': 0x030,'DFLT':0,'RW':'RW',
+                                   'COMMENTS':'TX/RX FIFO character data write/read',
+                                   'FIELDS':{
+                  'reserved':               {'r':( 8,31),'d':0},
+                  'fifo':                   {'r':( 0, 7),'d':0,  'c':'read/write FIFO character data'}}},
+           
       'baud_rate_div':            {'OFFS': 0x034,'DFLT':0xf,'RW':'RW',
                                    'COMMENTS':'Number of bit sample periods minus 1',
                                    'FIELDS':{

ezynqcfg.py

@@ -21,6 +21,7 @@ __version__ = "3.0+"
 __maintainer__ = "Andrey Filippov"
 __email__ = "andrey@elphel.com"
 __status__ = "Development"
+import os
 import struct
 import argparse # http://docs.python.org/2/howto/argparse.html
 
@@ -289,6 +290,7 @@ permit_undefined_bits=False
 force=True #False
 warn_notfit=True # False
 regs_masked=[]
+u_boot=ezynq_uboot.EzynqUBoot(raw_configs,args.verbosity)
 
 mio_regs=ezynq_mio.EzynqMIO(args.verbosity,QUALIFIER_CHAR,[],permit_undefined_bits) # does not use regs_masked
 mio_regs.process_mio(raw_configs,WARN)      # does not use regs_masked
@@ -312,32 +314,39 @@ ddr_mhz=clk.get_ddr_mhz()
     
         
 if MIO_HTML:
-    f=open(MIO_HTML,'w')
+    html_file=open(MIO_HTML,'w')
+    print 'Generating HTML output',os.path.abspath(MIO_HTML)
 else:
-    f=False
-
+    html_file=False
+u_boot.html_list_features(html_file)
 #output_slcr_lock(registers,f,False,MIO_HTML_MASK) #prohibited by RBL
-mio_regs.output_mio(f,MIO_HTML_MASK)
+mio_regs.output_mio(html_file,MIO_HTML_MASK)
 #  def process_mio(self,raw_configs,warn):
 #  def output_mio(self,f,MIO_HTML_MASK)
 #  setregs_mio(self,current_reg_sets,force=True):
 
-clk.html_list_clocks(f)
+clk.html_list_clocks(html_file)
 
     
 #output_mio(registers,f,mio,MIO_HTML_MASK)
 ddr.calculate_dependent_pars(ddr_mhz)
 ddr.pre_validate() # before applying default values (some timings should be undefined, not defaults)
 ddr.check_missing_features() #and apply default values
-ddr.html_list_features(f) #verify /fix values after defaults are applied
+ddr.html_list_features(html_file) #verify /fix values after defaults are applied
 
 #clk.calculate_dependent_pars()
-clk.html_list_features(f)
+clk.html_list_features(html_file)
 
 reg_sets=[]
 segments=[]
 reg_sets=mio_regs.setregs_mio(reg_sets,force) # reg Sets include now MIO
 segments.append({'TO':len(reg_sets),'RBL':True,'NAME':'MIO','TITLE':'MIO registers configuration'})
+led_debug_mio_pin= u_boot.features.get_par_value_or_none('LED_DEBUG')
+if not led_debug_mio_pin is None:
+    led_cp_1=u_boot.features.get_par_value_or_none('LED_CHECKPOINT_1')
+    if not led_cp_1 is None:
+        reg_sets=mio_regs.rbl_led_on_off(led_debug_mio_pin, led_cp_1, reg_sets)
+        segments.append({'TO':len(reg_sets),'RBL':True,'NAME':'RBL_LED','TITLE':'Setting debug LED during RBL to '+('OFF','ON')[led_cp_1]})
 #adding ddr registers
 if raw_config_value('CONFIG_EZYNQ_SKIP_DDR', raw_configs) is None:        
     ddr.ddr_init_memory(reg_sets,False,False)
@@ -353,11 +362,10 @@ segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'CLK','TITLE':'Clock regi
 #print 'Debug mode: CLK/PLL configuration by u-boot'
 reg_sets=clk.clocks_pll_bypass_off(reg_sets,force)
 segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'PLL','TITLE':'Registers to switch to PLL'})
-if not raw_config_value('CONFIG_EZYNQ_BOOT_DEBUG', raw_configs) is None:
+if u_boot.features.get_par_value_or_none('BOOT_DEBUG'):
     uart=ezynq_uart.EzynqUART()
     uart.parse_parameters(raw_configs,used_mio_interfaces,False)
     uart.check_missing_features()
-    
     uart_channel=uart.channel
     if not uart_channel is None:
         try:
@@ -372,11 +380,15 @@ else:
     uart_channel=None
 
 if not uart_channel is None:
-    uart.html_list_features(f)
-    # Generate UART initialization, putc and wait FIFO empty code
+    uart.html_list_features(html_file)
 
     reg_sets=uart.setup_uart(reg_sets,force=False,warn=False)
     segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'UART_INIT','TITLE':'Registers to initialize UART'})
+    
+    reg_sets_uart_extra=uart.set_uart_codes()
+    reg_sets.extend (reg_sets_uart_extra) # just to be listed, not to be loaded
+    segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'UART_XMIT','TITLE':'UART register tests sets to output debug data'})
+    
 if raw_config_value('CONFIG_EZYNQ_SKIP_DDR', raw_configs) is None:
     reg_sets=ddr.ddr_dci_calibrate(reg_sets,False,False)
     segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DCI','TITLE':'DDR DCI Calibration'})
@@ -389,13 +401,10 @@ reg_sets_lock_unlock=clk.generate_lock_unlock()
 reg_sets.extend (reg_sets_lock_unlock) # just to be listed, not to be loaded
 segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'SLCR_LOCK_UNLOCK','TITLE':'SLCR lock/unlock registers - listed out of sequence'})
 
-try:
-    led_mio_pin=int (raw_config_value('CONFIG_EZYNQ_LED_DEBUG', raw_configs),0)
-    reg_sets_led=mio_regs.generate_led_off_on(led_mio_pin)
+if not led_debug_mio_pin is None: 
+    reg_sets_led=mio_regs.generate_led_off_on(led_debug_mio_pin)
     reg_sets.extend (reg_sets_led) # just to be listed, not to be loaded
     segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'LED','TITLE':'registers/data to turn on/off debug LED - listed out of sequence'})
-except:
-    led_mio_pin=None 
 #    def generate_led_off_on(self, mio_pin):
 #CONFIG_EZYNQ_LED_DEBUG=47 # toggle LED during boot
 #CONFIG_EZYNQ_BOOT_DEBUG
@@ -426,27 +435,27 @@ for segment in segments:
     show_comments=    MIO_HTML_MASK & 0x200
     filter_fields=not MIO_HTML_MASK & 0x400
     all_used_fields= False
-    ezynq_registers.print_html_reg_header(f,
+    ezynq_registers.print_html_reg_header(html_file,
                                            segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]),
                                            show_bit_fields, show_comments, filter_fields)
 #   print segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]), start,end
 
-    ezynq_registers.print_html_registers(f,
+    ezynq_registers.print_html_registers(html_file,
                                           reg_sets[:end],
                                           start,
                                           show_bit_fields,
                                           show_comments,
                                           filter_fields,
                                           all_used_fields)
-    ezynq_registers.print_html_reg_footer(f)
+    ezynq_registers.print_html_reg_footer(html_file)
 
-if f:
-    f.write('<h4>Total number of registers set up in the RBL header is <b>'+str(num_rbl_regs)+"</b> of maximal 256</h4>")
+if html_file:
+    html_file.write('<h4>Total number of registers set up in the RBL header is <b>'+str(num_rbl_regs)+"</b> of maximal 256</h4>")
     if num_rbl_regs<len(reg_sets):
-        f.write('<h4>Number of registers set up in u-boot is <b>'+str(len(reg_sets)-num_rbl_regs)+"</b></h4>")
+        html_file.write('<h4>Number of registers set up in u-boot is <b>'+str(len(reg_sets)-num_rbl_regs)+"</b></h4>")
 #
 if MIO_HTML:
-    f.close
+    html_file.close
 #if args.verbosity >= 1:
 #    print registers
 image =[ 0 for k in range (0x8c0/4)]
@@ -476,9 +485,7 @@ if args.outfile:
 #     segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'UART_INIT','TITLE':'Registers to initialize UART'})
 #     segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DCI','TITLE':'DDR DCI Calibration'})
 #     segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'})
-
-u_boot=ezynq_uboot.EzynqUBoot(args.verbosity)
-
+#CONFIG_EZYNQ_UART_DEBUG_USE_LED
 if 'SLCR_LOCK_UNLOCK' in segment_dict: 
     u_boot.make_slcr_lock_unlock (reg_sets[segment_dict['SLCR_LOCK_UNLOCK']['FROM']:segment_dict['SLCR_LOCK_UNLOCK']['TO']])
 if 'LED' in segment_dict: 
@@ -489,7 +496,12 @@ if 'CLK' in segment_dict:
 if 'PLL' in segment_dict: 
     u_boot.pll_setup (reg_sets[segment_dict['PLL']['FROM']:segment_dict['PLL']['TO']],clk)
 if 'UART_INIT' in segment_dict: 
-    u_boot.uart_init (reg_sets[segment_dict['UART_INIT']['FROM']:segment_dict['UART_INIT']['TO']],clk)
+    u_boot.uart_init (reg_sets[segment_dict['UART_INIT']['FROM']:segment_dict['UART_INIT']['TO']])
+if 'UART_XMIT' in segment_dict: 
+    u_boot.uart_transmit (reg_sets[segment_dict['UART_XMIT']['FROM']:segment_dict['UART_XMIT']['TO']])
+    u_boot.make_ddrc_register_dump()
+    u_boot.make_slcr_register_dump()
+#if not u_boot.features.get_par_value_or_none('BOOT_DEBUG') is None:
     
 if 'DCI' in segment_dict: 
     u_boot.dci_calibration(reg_sets[segment_dict['DCI']['FROM']:segment_dict['DCI']['TO']],ddr)

test.mk

-CONFIG_EZYNQ_BOOT_DEBUG=y # configure UARTx and send register dumps there
-CONFIG_EZYNQ_LED_DEBUG=47 # toggle LED during boot
+CONFIG_EZYNQ_BOOT_DEBUG = y # configure UARTx and send register dumps there
+CONFIG_EZYNQ_LED_DEBUG = 47 # toggle LED during boot
+CONFIG_EZYNQ_UART_DEBUG_USE_LED = y # turn on/off LED while waiting for transmit FIFO not full
+
+CONFIG_EZYNQ_DUMP_SLCR_EARLY = y # Dump SLCR registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)
+CONFIG_EZYNQ_DUMP_DDRC_EARLY = y # Dump DDRC registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)
+CONFIG_EZYNQ_DUMP_SLCR_LATE = y # Dump SLCR registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)
+CONFIG_EZYNQ_DUMP_DDRC_LATE = y # Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)
+
+#Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG to be set
+#If defined, each can be 0,1, ON or OFF
+CONFIG_EZYNQ_LED_CHECKPOINT_1  = ON  # in RBL setup, as soon as MIO is programmed 
+#CONFIG_EZYNQ_LED_CHECKPOINT_2  = OFF # First after getting to user code 
+#CONFIG_EZYNQ_LED_CHECKPOINT_3  = ON  # After setting clock registers 
+#CONFIG_EZYNQ_LED_CHECKPOINT_4  = OFF # After PLL bypass is OFF
+#CONFIG_EZYNQ_LED_CHECKPOINT_5  = ON  # After UART is programmed
+CONFIG_EZYNQ_LED_CHECKPOINT_6  = OFF # After DCI is calibrated
+CONFIG_EZYNQ_LED_CHECKPOINT_7  = ON  # After DDR is initialized
+CONFIG_EZYNQ_LED_CHECKPOINT_8  = OFF # Before relocation to DDR (to 0x4000000+ )
+CONFIG_EZYNQ_LED_CHECKPOINT_9  = ON  # After  relocation to DDR (to 0x4000000+ )
+CONFIG_EZYNQ_LED_CHECKPOINT_10 = OFF # Before remapping OCM0-OCM2 high
+CONFIG_EZYNQ_LED_CHECKPOINT_11 = ON  # After remapping OCM0-OCM2 high
+CONFIG_EZYNQ_LED_CHECKPOINT_12 = OFF # Before leaving lowlevel_init()
+ 
+
 CONFIG_EZYNQ_UART1_BAUD_RATE=115200
 
 #Configuration for the microzed board