# reg ctrl_reg4 0x1610 - all 3 times (default) - keeping
ddrc_register_set.set_bitfields('ctrl_reg4',(
('dfi_t_ctrlupd_interval_max_x1024',0x16),# 0x16 - maximal time between DFI update requests in 1024 clocks
('dfi_t_ctrlupd_interval_min_x1024',0x10),# 0x10 - minimal time between DFI update requests in 1024 clocks
),force,warn)
# 'rd_dll_force1': {'OFFS': 0x070},
# 'wr_ratio_reg': {'OFFS': 0x074},
# reg ctrl_reg5 0x466111 - only 2 times set, but same default
#CKE= self.features.get_par_value('CKE') # 4 defined earlier
CKSRE=self.features.get_par_value('CKSRE')# 6
CKSRX=self.features.get_par_value('CKSRX')# 6
ifis_DDR3:
t_ckesr=CKE+1# contradicts dram_param_reg1 in actual settings - both have 0x4, but one - CKE, another CKE+1. Better safe than sorry, and SR exit is not that often
t_cksrx=CKSRX
t_cksre=CKSRE
elifis_DDR2:
t_ckesr=CKE
t_cksrx=1
t_cksre=1
elifis_LPDDR2:
t_ckesr=CKSRX
t_cksrx=2
t_cksre=2
dfi_t_dram_clk_enable=1# keeping defaults==actual for DDR3 - not clear what specs to use
dfi_t_dram_clk_disable=1# keeping defaults==actual for DDR3 - not clear what specs to use
dfi_t_ctrl_delay=1# keeping defaults==actual for DDR3 - not clear what specs to use
ddrc_register_set.set_bitfields('ctrl_reg5',(
('reserved1',0),# 0
('reg_ddrc_t_ckesr',t_ckesr),# 0x4->5 Min CKE low for self refresh, recomm.: DDR3:tCKE+1,DDR2:tCKE,LPDDR2:tCKESR
('reg_ddrc_t_cksrx',t_cksrx),# 0x6 CK valid before self refresh exit, recomm. DDR3:tCKSRX,DDR2:1,LPDDR2:2
('reg_ddrc_t_cksre',t_cksre),# 0x6 CK valid after self refresh entry, recomm. DDR3:tCKSRE,DDR2:1,LPDDR2:2
('reg_ddrc_dfi_t_dram_clk_enable',dfi_t_dram_clk_enable),# 0x1 deassert dfi_dram_clock disable to PHY clock enable in DFI clock cycles
('reg_ddrc_dfi_t_dram_clk_disable',dfi_t_dram_clk_disable),# 0x1 assert dfi_dram_clock disable to PHY clock disable in DFI clock cycles
('reg_ddrc_dfi_t_ctrl_delay',dfi_t_ctrl_delay),# 0x1 ssert/deassert DFI control signals to PHY-DRAM control signals
),force,warn)
# reg ctrl_reg6 0x32222 - only 2 times set, but same default
# Keeping actual/defaults - all recommendations are listed for LPDDR2 only (tXP+2 for DDR3 would be 6 - does not match actual).
ddrc_register_set.set_bitfields('ctrl_reg6',(
('reserved1',0),# 0
('reg_ddrc_t_ckcsx',0x3),# 0x3 Clock stable before exiting clock stop. Recommended for LPDDR2: tXP+2
('reg_ddrc_t_ckdpdx',0x2),# 0x2 Clock stable before Deep Power Down exit. Recommended for LPDDR2: 2
('reg_ddrc_t_ckdpde',0x2),# 0x2 Maintain clock after Deep Power Down entry. Recommended for LPDDR2: 2
('reg_ddrc_t_ckpdx',0x2),# 0x2 Clock stable before Power Down exit. Recommended for LPDDR2: 2
('reg_ddrc_t_ckpde',0x2),# 0x2 Maintain clock after Power Down entry. Recommended for LPDDR2: 2
# 'reg_ddrc_addrmap_row_b15': {'r':(24,27),'d':0xF,'c':'Selects address bits for row. addr. bit 15, Valid 0..5 and 15, int. base=24 if 15 - address bit 15 is set to 0'}, # 0xf
# 'reg_ddrc_addrmap_row_b14': {'r':(20,23),'d':0xF,'c':'Selects address bits for row. addr. bit 14, Valid 0..6 and 15, int. base=23 if 15 - address bit 14 is set to 0'}, # 0x6
# 'reg_ddrc_addrmap_row_b13': {'r':(16,19),'d':0x5,'c':'Selects address bits for row. addr. bit 13, Valid 0..7 and 15, int. base=22 if 15 - address bit 13 is set to 0'}, # 0x6
# 'reg_ddrc_addrmap_row_b12': {'r':(12,15),'d':0x5,'c':'Selects address bits for row. addr. bit 12, Valid 0..8 and 15, int. base=21 if 15 - address bit 12 is set to 0'}, # 0x6
# 'reg_ddrc_addrmap_row_b2_11': {'r':( 8,11),'d':0x5,'c':'Selects address bits for row. addr. bits 2 to 11, Valid 0..11, int. base=11 (for a2) to 20 (for a 11)'}, # 0x6
# 'reg_ddrc_addrmap_row_b1': {'r':( 4, 7),'d':0x5,'c':'Selects address bits for row. addr. bit 1, Valid 0..11, int. base=10'}, # 0x6
# 'reg_ddrc_addrmap_row_b0': {'r':( 0, 3),'d':0x5,'c':'Selects address bits for row. addr. bit 0, Valid 0..11, int. base=9'}}}, # 0x6
'reg_ddrc_dis_collision_page_opt':{'r':(10,10),'d':0,'c':'Disable autoprecharge for collisions (write+write or read+write to the same address) when reg_ddrc_dis_wc==1'},
'reg_ddrc_dis_collision_page_opt':{'r':(10,10),'d':0,'c':'Disable autoprecharge for collisions (write+write or read+write to the same address) when reg_ddrc_dis_wc==1'},
'reg_ddrc_skip_ocd':{'r':(9,9),'d':0x1,'c':'should be 1, 0 is not supported. 1 - skip OCD adjustment step during DDR2 init, use OCD_Default and OCD_exit'},
'reg_ddrc_skip_ocd':{'r':(9,9),'d':0x1,'c':'should be 1, 0 is not supported. 1 - skip OCD adjustment step during DDR2 init, use OCD_Default and OCD_exit'},
