Commit e368919b authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Finished PLL/clocks configuration by the RBL register setup

parent 82bd6499

ezynq_clk.py

+833 −96

File changed.

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ezynq_clkcfg_defs.py

+8 −8
Original line number Diff line number Diff line
@@ -77,14 +77,14 @@ CLK_CFG_DEFS=[ 
              

    {'NAME':'ARM_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_ARM_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'ARM',

                'DESCRIPTION':'ARM CPU clock source (normally ARM PLL)'},

    {'NAME':'DDR_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_DDR_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'DDR',

                'DESCRIPTION':'DDR (DDR2x, DDR3x) clock source (normally DDR PLL)'},

    {'NAME':'DDR_DCI_SRC',   'CONF_NAME':'CONFIG_EZYNQ_CLK_DDR_DCI_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'DDR',

                'DESCRIPTION':'DDR DCI clock source (normally DDR PLL)'},

    {'NAME':'DDR_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_DDR_SRC','TYPE':('DDR',),'MANDATORY':False,'DERIVED':False,'DEFAULT':'DDR',

                'DESCRIPTION':'DDR (DDR2x, DDR3x) clock source (Only valid DDR PLL)'},

    {'NAME':'DDR_DCI_SRC',   'CONF_NAME':'CONFIG_EZYNQ_CLK_DDR_DCI_SRC','TYPE':('DDR',),'MANDATORY':False,'DERIVED':False,'DEFAULT':'DDR',

                'DESCRIPTION':'DDR DCI clock source (only valid DDR PLL)'},

    {'NAME':'SMC_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_SMC_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',

                'DESCRIPTION':'Static memory controller clock source (normally IO PLL)'},

    {'NAME':'QSPI_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_QSPI_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',

                'DESCRIPTION':'Quad SPI memory controller clock source (normally IO PLL)'},

    {'NAME':'QSPI_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_QSPI_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'ARM',

                'DESCRIPTION':'Quad SPI memory controller clock source (normally ARM PLL)'},

    {'NAME':'GIGE0_SRC',      'CONF_NAME':'CONFIG_EZYNQ_CLK_GIGE0_SRC','TYPE':('ARM','DDR','IO','EMIO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',

                'DESCRIPTION':'GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO)'},

    {'NAME':'GIGE1_SRC',      'CONF_NAME':'CONFIG_EZYNQ_CLK_GIGE1_SRC','TYPE':('ARM','DDR','IO','EMIO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',
@@ -99,7 +99,7 @@ CLK_CFG_DEFS=[ 
                'DESCRIPTION':'CAN controller clock source (normally IO PLL)'},

    {'NAME':'PCAP_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_PCAP_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',

                'DESCRIPTION':'PCAP controller clock source (normally IO PLL)'},

    {'NAME':'TRACE_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_TRACE_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',

    {'NAME':'TRACE_SRC',       'CONF_NAME':'CONFIG_EZYNQ_CLK_TRACE_SRC','TYPE':('ARM','DDR','IO','EMIO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',

                'DESCRIPTION':'Trace Port clock source (normally IO PLL)'},



# performance data, final values (overwrites calculated)
@@ -191,7 +191,7 @@ CLK_CFG_DEFS=[ 
#CONFIG_EZYNQ_CLK_DDR_SRC =       DDR # DDR (DDR2x, DDR3x) clock source (normally DDR PLL)

#CONFIG_EZYNQ_CLK_DDR_DCI_SRC =   DDR # DDR DCI clock source (normally DDR PLL)

#CONFIG_EZYNQ_CLK_SMC_SRC =        IO # Static memory controller clock source (normally IO PLL)

#CONFIG_EZYNQ_CLK_QSPI_SRC =       IO # Quad SPI memory controller clock source (normally IO PLL)

#CONFIG_EZYNQ_CLK_QSPI_SRC =      ARM # Quad SPI memory controller clock source (normally ARM PLL)

#CONFIG_EZYNQ_CLK_GIGE0_SRC =      IO # GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO)

#CONFIG_EZYNQ_CLK_GIGE1_SRC =      IO # GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO)

#CONFIG_EZYNQ_CLK_SDIO_SRC =       IO # SDIO controller clock source (normally IO PLL)

ezynq_ddr.py

+3 −3
Original line number Diff line number Diff line
@@ -262,10 +262,10 @@ class EzynqDDR: 
        ddrc_register_set=  self.ddrc_register_set

        ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state

        

        self.ddr_init_ddriob(force,warn) # will program to sequence 'MAIN'

        self.ddr_init_ddriob(force,warn)

        regs1=ddriob_register_set.get_register_sets(True,True)

        ddrc_register_set.set_initial_state(regs1, True)# add

        self.ddr_init_ddrc(force,warn) # will program to sequence 'MAIN'

        self.ddr_init_ddrc(force,warn)

        return ddrc_register_set.get_register_sets(True,True)



    def ddr_init_ddrc(self,force=False,warn=False): # will program to sequence 'MAIN'

ezynq_slcr_clk_def.py

+13 −13
Original line number Diff line number Diff line
@@ -120,7 +120,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently 
                                   'COMMENTS':'CPU clock control',

                                   'FIELDS':{

                  'reserved1':                {'r':(29,31),'d':0,     'c':'reserved'},

                  'cpu_peri_clkact':          {'r':(28,28),'d':0x1,   'c':'Clock active (0 - disabled)'},         # 1

                  'cpu_peri_clkact':          {'r':(28,28),'d':0x1,   'c':'Peripheral clock active (0 - disabled)'},# 1

                  'cpu_1x_clkact':            {'r':(27,27),'d':0x1,   'c':'CPU-1x clock active (0 - disabled)'},    # 1

                  'cpu_2x_clkact':            {'r':(26,26),'d':0x1,   'c':'CPU-2x clock active (0 - disabled)'},    # 1

                  'cpu_3x2x_clkact':          {'r':(25,25),'d':0x1,   'c':'CPU-3x2x clock active (0 - disabled)'},  # 1
@@ -132,16 +132,16 @@ SLCR_CLK_DEFS={ #not all fields are defined currently 
                  'reserved4':                {'r':( 6, 7),'d':0,     'c':'reserved'}}},



      'ddr_clk_ctrl':             {'OFFS': 0x124,'DFLT':0x18400003,'RW':'RW', # 0xc200003

                                   'COMMENTS':'CPU clock control',

                                   'COMMENTS':'DDR_3x (including PHY) and DDR_2X clock control',

                                   'FIELDS':{

                  'ddr_2x_clk_divisor':       {'r':(26,31),'d':0x6,   'c':'Frequency divisor for ddr_2x clk'},  # 0x3

                  'ddr_3x_clk_divisor':       {'r':(20,25),'d':0x4,   'c':'Frequency divisor for ddr_3x clk'},  # 0x2

                  'reserved1':                {'r':( 2,19),'d':0,     'c':'reserved'},

                  'cpu_2x_clkact':            {'r':( 1, 1),'d':0x1,   'c':'1 - ddr_2x clk enabled (0 - disabled)'},  # 0x1

                  'cpu_3x_clkact':            {'r':( 0, 0),'d':0x1,   'c':'1 - ddr_3x clk enabled (0 - disabled)'}}},# 0x1

                  'ddr_2x_clkact':            {'r':( 1, 1),'d':0x1,   'c':'1 - ddr_2x clk enabled (0 - disabled)'},  # 0x1

                  'ddr_3x_clkact':            {'r':( 0, 0),'d':0x1,   'c':'1 - ddr_3x clk enabled (0 - disabled)'}}},# 0x1



      'dci_clk_ctrl':             {'OFFS': 0x128,'DFLT':0x18400003,'RW':'RW', # 0x302301

                                   'COMMENTS':'CPU clock control',

                                   'COMMENTS':'DDR DCI clock control',

                                   'FIELDS':{

                  'reserved1':                {'r':(26,31),'d':0,     'c':'reserved'},

                  'divisor1':                 {'r':(20,25),'d':0x1e,  'c':'Frequency divisor, second stage'},       # 0x3
@@ -151,7 +151,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently 
                  'clkact':                   {'r':( 0, 0),'d':0x1,   'c':'1 - dci clock enabled (0 - disabled)'}}},# 0x1



      'aper_clk_ctrl':            {'OFFS': 0x12c,'DFLT':0x01ffcccd, 'RW':'RW', # 0x01ec044d (set after peripherals)

                                   'COMMENTS':'CPU clock control',

                                   'COMMENTS':'AMBA peripherals clock control',

                                   'FIELDS':{

                  'reserved1':                {'r':(25,31),'d':0,     'c':'reserved'},

                  'smc_cpu_1x_clkact':        {'r':(24,24),'d':0x1,   'c':'SMC AMBA clock control (1- enabled, 0- disabled)'},        # 0x1
@@ -315,10 +315,10 @@ SLCR_CLK_DEFS={ #not all fields are defined currently 
                  'can1_ref_sel':             {'r':(22,22),'d':0,    'c':'CAN1 reference clock selection: 0: from internal PLL, 1 - from MIO based on can1_mux selection'},

                  'can1_mux':                 {'r':(16,21),'d':0,    'c':'CAN1 MIO pin selection (valid: 0..53)'},

                  'reserved2':                {'r':( 7,15),'d':0,    'c':'reserved'},

                  'can1_ref_sel':             {'r':( 6, 6),'d':0,    'c':'CAN0 reference clock selection: 0: from internal PLL, 1 - from MIO based on can0_mux selection'},

                  'can1_mux':                 {'r':( 0, 5),'d':0,    'c':'CAN0 MIO pin selection (valid: 0..53)'}}},

                  'can0_ref_sel':             {'r':( 6, 6),'d':0,    'c':'CAN0 reference clock selection: 0: from internal PLL, 1 - from MIO based on can0_mux selection'},

                  'can0_mux':                 {'r':( 0, 5),'d':0,    'c':'CAN0 MIO pin selection (valid: 0..53)'}}},



      'spi_clk_ctrl':             {'OFFS': 0x164,'DFLT':0xf03,'RW':'RW', # Never set

      'dbg_clk_ctrl':             {'OFFS': 0x164,'DFLT':0xf03,'RW':'RW', # Never set

                                   'COMMENTS':'SoC debug clock control',

                                   'FIELDS':{

                  'reserved1':                {'r':(14,31),'d':0,    'c':'reserved'},

ezynqcfg.py

+59 −4
Original line number Diff line number Diff line
@@ -278,6 +278,8 @@ def write_image(image,name): 
    bf.close()

         

#=========================

if not args.verbosity:

    args.verbosity=0

raw_configs=read_config(args.configs)

raw_options={n['KEY']:n['VALUE'] for n in raw_configs}

permit_undefined_bits=False
@@ -295,7 +297,7 @@ ddr_type=ddr.get_ddr_type() 
used_mio_interfaces=mio_regs.get_used_interfaces()



#clk=ezynq_clk.EzynqClk(regs_masked,ddr_type,permit_undefined_bits=False,force=False,warn=False)

clk=ezynq_clk.EzynqClk([],ddr_type,used_mio_interfaces,permit_undefined_bits,force,warn_notfit) # will it verify memory type is set?

clk=ezynq_clk.EzynqClk(args.verbosity,[],ddr_type,used_mio_interfaces,permit_undefined_bits,force,warn_notfit) # will it verify memory type is set?

clk.parse_parameters(raw_configs)



clk.calculate_dependent_pars() # will calculate DDR clock, needed for ddr.calculate_dependent_pars()
@@ -335,21 +337,74 @@ num_mio_regs=len(reg_sets) 


#adding ddr registers

ddr.ddr_init_memory(reg_sets,False,False)

#Collecting registers for output

reg_sets=ddr.get_new_register_sets() # mio, ddr

num_ddr_regs=len(reg_sets)-num_mio_regs



reg_sets=ddr.get_new_register_sets() #all - mio and ddr



#initialize clocks

#   def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False):

 

clk.clocks_rbl_setup(reg_sets,force) # reg Sets include now MIO and CLK

reg_sets=clk.get_new_register_sets() # mio, ddr and clk



num_clk_regs=len(reg_sets)-num_mio_regs-num_ddr_regs





# #adding ddr registers

# ddr.ddr_init_memory(reg_sets,False,False)

# #Collecting registers for output

# 

# reg_sets=ddr.get_new_register_sets() #all - mio,clk and ddr





ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)



#ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

ezynq_registers.print_html_reg_footer(f)





ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs:num_mio_regs+num_ddr_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

ezynq_registers.print_html_reg_footer(f)



ezynq_registers.print_html_reg_header(f, 'CLOCK registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs+num_ddr_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

ezynq_registers.print_html_reg_footer(f)







# #initialize clocks

# #   def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False):

#  

# clk.clocks_rbl_setup(reg_sets,force) # reg Sets include now MIO and CLK

# reg_sets=clk.get_new_register_sets() # mio and clk

# num_clk_regs=len(reg_sets)-num_mio_regs

# 

# 

# #adding ddr registers

# ddr.ddr_init_memory(reg_sets,False,False)

# #Collecting registers for output

# 

# reg_sets=ddr.get_new_register_sets() #all - mio,clk and ddr

# 

# 

# ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

# 

# #ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

# ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

# ezynq_registers.print_html_reg_footer(f)

# 

# ezynq_registers.print_html_reg_header(f, 'CLOCK registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

# ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs: num_mio_regs+num_clk_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

# ezynq_registers.print_html_reg_footer(f)

# 

# 

# ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

# ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs+num_clk_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)

# ezynq_registers.print_html_reg_footer(f)





#TODO: Need to be modified for the new format

# if 'CONFIG_EZYNQ_UART_LOOPBACK_0' in raw_options: uart_remote_loopback(registers,f, 0,MIO_HTML_MASK)

# if 'CONFIG_EZYNQ_UART_LOOPBACK_1' in raw_options: uart_remote_loopback(registers,f, 1,MIO_HTML_MASK)