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ezynq
Commit e368919b authored by Andrey Filippov's avatar Andrey Filippov
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Finished PLL/clocks configuration by the RBL register setup

parent 82bd6499
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Showing with 917 additions and 125 deletions
ezynq_clk.py
View file @ e368919b
...@@ -46,9 +46,25 @@ CLK_TEMPLATE=[ ...@@ -46,9 +46,25 @@ CLK_TEMPLATE=[
{'NAME':'FPGA1', 'VALUE':'FPGA1_MHZ', 'SOURCE':'FPGA1_SRC', 'DIV2':True, 'USED':True, 'WEIGHT':1.0}, # source can be set to None {'NAME':'FPGA1', 'VALUE':'FPGA1_MHZ', 'SOURCE':'FPGA1_SRC', 'DIV2':True, 'USED':True, 'WEIGHT':1.0}, # source can be set to None
{'NAME':'FPGA2', 'VALUE':'FPGA2_MHZ', 'SOURCE':'FPGA2_SRC', 'DIV2':True, 'USED':True, 'WEIGHT':1.0}, # source can be set to None {'NAME':'FPGA2', 'VALUE':'FPGA2_MHZ', 'SOURCE':'FPGA2_SRC', 'DIV2':True, 'USED':True, 'WEIGHT':1.0}, # source can be set to None
{'NAME':'FPGA3', 'VALUE':'FPGA3_MHZ', 'SOURCE':'FPGA3_SRC', 'DIV2':True, 'USED':True, 'WEIGHT':1.0}, # source can be set to None {'NAME':'FPGA3', 'VALUE':'FPGA3_MHZ', 'SOURCE':'FPGA3_SRC', 'DIV2':True, 'USED':True, 'WEIGHT':1.0}, # source can be set to None
# Same frequency/derived clocks
{'NAME':'CPU_1X', 'VALUE':6, 'SOURCE':'ARM', 'DIV2':False,'USED':True, 'WEIGHT':0.0},
{'NAME':'CPU_2X', 'VALUE':3, 'SOURCE':'ARM', 'DIV2':False,'USED':True, 'WEIGHT':0.0},
{'NAME':'SDIO0', 'VALUE':1, 'SOURCE':'SDIO', 'DIV2':False,'USED':(('SDIO',0),), 'WEIGHT':0.0},
{'NAME':'SDIO1', 'VALUE':1, 'SOURCE':'SDIO', 'DIV2':False,'USED':(('SDIO',1),), 'WEIGHT':0.0},
{'NAME':'UART0', 'VALUE':1, 'SOURCE':'UART', 'DIV2':False,'USED':(('UART',0),), 'WEIGHT':0.0},
{'NAME':'UART1', 'VALUE':1, 'SOURCE':'UART', 'DIV2':False,'USED':(('UART',1),), 'WEIGHT':0.0},
{'NAME':'SPI0', 'VALUE':1, 'SOURCE':'SPI', 'DIV2':False,'USED':(('SPI',0),), 'WEIGHT':0.0},
{'NAME':'SPI1', 'VALUE':1, 'SOURCE':'SPI', 'DIV2':False,'USED':(('SPI',1),), 'WEIGHT':0.0},
{'NAME':'I2C0', 'VALUE':1, 'SOURCE':'CPU_1X', 'DIV2':False,'USED':(('I2C',0),), 'WEIGHT':0.0},
{'NAME':'I2C1', 'VALUE':1, 'SOURCE':'CPU_1X', 'DIV2':False,'USED':(('I2C',1),), 'WEIGHT':0.0},
{'NAME':'CAN0', 'VALUE':1, 'SOURCE':'CPU_1X', 'DIV2':False,'USED':(('CAN',0),), 'WEIGHT':0.0},
{'NAME':'CAN1', 'VALUE':1, 'SOURCE':'CPU_1X', 'DIV2':False,'USED':(('CAN',1),), 'WEIGHT':0.0},
] ]
class EzynqClk: class EzynqClk:
def __init__(self,regs_masked,ddr_type,used_mio_interfaces,permit_undefined_bits=False,force=False,warn=False): def __init__(self, verbosity,regs_masked,ddr_type,used_mio_interfaces,permit_undefined_bits=False,force=False,warn=False):
self.verbosity=verbosity
self.SLCR_CLK_DEFS= ezynq_slcr_clk_def.SLCR_CLK_DEFS self.SLCR_CLK_DEFS= ezynq_slcr_clk_def.SLCR_CLK_DEFS
self.CLK_CFG_DEFS = ezynq_clkcfg_defs.CLK_CFG_DEFS self.CLK_CFG_DEFS = ezynq_clkcfg_defs.CLK_CFG_DEFS
self.features=ezynq_feature_config.EzynqFeatures(self.CLK_CFG_DEFS,0) #CLK_CFG_DEFS self.features=ezynq_feature_config.EzynqFeatures(self.CLK_CFG_DEFS,0) #CLK_CFG_DEFS
...@@ -74,7 +90,7 @@ class EzynqClk: ...@@ -74,7 +90,7 @@ class EzynqClk:
'DDR':self._get_valid_pll_fdiv(), 'DDR':self._get_valid_pll_fdiv(),
'IO': self._get_valid_pll_fdiv()} 'IO': self._get_valid_pll_fdiv()}
self.clk_dict={} self.clk_dict={}
for i,c in enumerate(CLK_TEMPLATE): for c in CLK_TEMPLATE:
self.clk_dict[c['NAME']]=c self.clk_dict[c['NAME']]=c
def parse_parameters(self,raw_configs): def parse_parameters(self,raw_configs):
self.features.parse_features(raw_configs) self.features.parse_features(raw_configs)
...@@ -156,6 +172,8 @@ class EzynqClk: ...@@ -156,6 +172,8 @@ class EzynqClk:
return valid_fdiv return valid_fdiv
def setup_clocks(self): def setup_clocks(self):
# print 'self.verbosity=',self.verbosity
if self.verbosity>2 :
for ifc in self.used_mio_interfaces: for ifc in self.used_mio_interfaces:
print ifc print ifc
self.get_clk_requirements(self.used_mio_interfaces) self.get_clk_requirements(self.used_mio_interfaces)
...@@ -229,14 +247,20 @@ class EzynqClk: ...@@ -229,14 +247,20 @@ class EzynqClk:
# valid_div6x6= sorted({x*y for x in range(1,64) for y in range(1,64)}) # valid_div6x6= sorted({x*y for x in range(1,64) for y in range(1,64)})
self.f_in=self.features.get_par_value_or_default('PS_MHZ') self.f_in=self.features.get_par_value_or_default('PS_MHZ')
clock_reqs={'ARM':[],'DDR':[],'IO':[]} clock_reqs={'ARM':[],'DDR':[],'IO':[]}
self.iface_divs={} # for each name - PLL, divisor
# self.secondary_clocks={}
for template in CLK_TEMPLATE: for template in CLK_TEMPLATE:
name= template['NAME'] name= template['NAME']
div2= template['DIV2'] div2= template['DIV2']
weight= template['WEIGHT'] weight= template['WEIGHT']
value=template['VALUE']
source=template['SOURCE']
is_secondary=isinstance(template['VALUE'],int)
if not is_secondary:
value= self.features.get_par_value_or_default(template['VALUE']) value= self.features.get_par_value_or_default(template['VALUE'])
if value==0: if value==0:
continue continue
source= self.features.get_par_value_or_default(template['SOURCE']) source= self.features.get_par_value_or_default(source)
if not template['USED'] is True: if not template['USED'] is True:
ifc={i[0]:set() for i in template['USED']} ifc={i[0]:set() for i in template['USED']}
# print 'ifc=',ifc # print 'ifc=',ifc
...@@ -250,8 +274,20 @@ class EzynqClk: ...@@ -250,8 +274,20 @@ class EzynqClk:
break break
pass pass
else: else:
if source != 'EMIO':
continue # no MIO interface uses this clock continue # no MIO interface uses this clock
if source in clock_reqs: else:
pass #for Ethernet controllers connected to EMIO
value=0 # something else?
is_secondary=True
#for trace port that can be EMIO
if source == 'EMIO':
value=0 # something else?
is_secondary=True
if is_secondary:
self.iface_divs[name]={'SOURCE':source,'VALUE':value} #no 'PLL' field
elif source in clock_reqs:
if name == 'ARM': if name == 'ARM':
valid_divs=self.arm_valid_div6 valid_divs=self.arm_valid_div6
elif name == 'DDR': elif name == 'DDR':
...@@ -268,7 +304,6 @@ class EzynqClk: ...@@ -268,7 +304,6 @@ class EzynqClk:
# print i # print i
# for n in c: # for n in c:
# print ' ',n,':',c[n] # print ' ',n,':',c[n]
self.iface_divs={} # for each name - PLL, divisor
self.pll_fdivs={} self.pll_fdivs={}
for pll in clock_reqs: # clocks belonging to the same PLL for pll in clock_reqs: # clocks belonging to the same PLL
pll_errs=[] pll_errs=[]
...@@ -299,13 +334,27 @@ class EzynqClk: ...@@ -299,13 +334,27 @@ class EzynqClk:
div2,div=self.div_second_stage(div) div2,div=self.div_second_stage(div)
self.iface_divs[name]['DIV']= div self.iface_divs[name]['DIV']= div
self.iface_divs[name]['DIV2']=div2 self.iface_divs[name]['DIV2']=div2
self.iface_divs['CPU_1X']['FREQ']= self.iface_divs['ARM']['FREQ']/(4,6)[self.is621]
self.iface_divs['CPU_2X']['FREQ']= self.iface_divs['ARM']['FREQ']/(1,3)[self.is621]
for name in self.iface_divs:
clk=self.iface_divs[name]
if (not 'PLL' in clk ) and (not 'FREQ' in clk):
self.iface_divs[name]['FREQ']=self.iface_divs[self.iface_divs[name]['SOURCE']]['FREQ'] # same frequency - possible to use 'VALUE' as scale
print 'pll_fdivs=', self.pll_fdivs
print 'iface_divs='#,iface_divs
for iface in self.iface_divs:
print iface,': ',self.iface_divs[iface]
def html_list_clocks(self,html_file): def html_list_clocks(self,html_file):
def list_with_children(name):
result = [name]
for kid_name in self.iface_divs:
if not 'PLL' in self.iface_divs[kid_name]:
try:
# print name,' ---> ',kid_name,', source=',self.iface_divs[kid_name]['SOURCE']
if self.iface_divs[kid_name]['SOURCE']==name:
result.extend(list_with_children(kid_name))
except:
pass
return result
html_file.write('<h2>System PLL (input clock - %.3f MHz)</h2>'%self.f_in) html_file.write('<h2>System PLL (input clock - %.3f MHz)</h2>'%self.f_in)
html_file.write('<table border="1">') html_file.write('<table border="1">')
html_file.write(' <tr><th>PLL name</th><th>Frequency</th><th>FDIV</th></tr>\n') html_file.write(' <tr><th>PLL name</th><th>Frequency</th><th>FDIV</th></tr>\n')
...@@ -323,10 +372,13 @@ class EzynqClk: ...@@ -323,10 +372,13 @@ class EzynqClk:
html_file.write('<h2>System Clocks</h2>') html_file.write('<h2>System Clocks</h2>')
html_file.write('<table border="1">') html_file.write('<table border="1">')
html_file.write(' <tr><th>Name</th><th>Frequency</th><th>Target</th><th>Error</th><th>PLL</th><th>div 1</th><th>div 2</th><th>Config. name</th><th>Comments</th></tr>\n') html_file.write(' <tr><th>Name</th><th>Frequency</th><th>Target</th><th>Error</th><th>PLL</th><th>div 1</th><th>div 2</th><th>Config. name</th><th>Comments</th></tr>\n')
#TODO - show secondary clocks together with the main ones (frequency only if different from source. Use rowspan
# self.iface_divs[name]={'SOURCE':source,'VALUE':value, 'FREQ':frequency} #no 'PLL' field
#CLK_TEMPLATE #CLK_TEMPLATE
for line in CLK_TEMPLATE: for line in CLK_TEMPLATE:
name=line['NAME'] name=line['NAME']
if name in self.iface_divs: if (name in self.iface_divs) and ('PLL' in self.iface_divs[name]):
iface=self.iface_divs[name] iface=self.iface_divs[name]
freq=iface['FREQ'] freq=iface['FREQ']
target=iface['TARGET'] target=iface['TARGET']
...@@ -339,87 +391,772 @@ class EzynqClk: ...@@ -339,87 +391,772 @@ class EzynqClk:
div2='%i'%iface['DIV2'] div2='%i'%iface['DIV2']
except: except:
div2='-' div2='-'
children=list_with_children(name)
html_file.write(' <tr><th>%s</th><td>%.3f MHz</td><td>%.3f MHz</td><td>%.2f%%</td><td>%s</td><td>%i</td><td>%s</td><td>%s</td><td>%s</td></tr>'%( html_file.write(' <tr><th>%s</th><td>%.3f MHz</td><td>%.3f MHz</td><td>%.2f%%</td><td>%s</td><td>%i</td><td>%s</td><td>%s</td><td>%s</td></tr>'%(
name, freq, target, 100*rel_err, pll, div1, div2, conf_name, description)) name, freq, target, 100*rel_err, pll, div1, div2, conf_name, description))
html_file.write(' </tr>') html_file.write(' </tr>')
for kid_name in children[1:]:
kid_freq=self.iface_divs[kid_name]['FREQ']
source=self.iface_divs[kid_name]['SOURCE']
html_file.write(' <tr><th>%s</th><td>%.3f MHz</td><td colspan="7" align="center">Derived from %s</td></tr>'%(kid_name, kid_freq,source))
# if len(children)>1:
# print name, "has children=",children
# elif name in self.iface_divs:
# print 'dependent ',name,' -> ',self.iface_divs[name]
html_file.write('</table>') html_file.write('</table>')
def get_ddr_mhz(self): def get_ddr_mhz(self):
return self.f_in*self.pll_fdivs[self.iface_divs['DDR']['PLL']]/self.iface_divs['DDR']['DIV'] return self.f_in*self.pll_fdivs[self.iface_divs['DDR']['PLL']]/self.iface_divs['DDR']['DIV']
############# Main clock settings ############# def get_new_register_sets(self):
#CONFIG_EZYNQ_CLK_PS_MHZ = 33.333333 # PS_CLK System clock input frequency (MHz) return self.clk_register_set.get_register_sets(True,True)
#CONFIG_EZYNQ_CLK_DDR_MHZ = 533.333333 # DDR clock frequency - DDR_3X (MHz)
#CONFIG_EZYNQ_CLK_ARM_MHZ = 667 # ARM CPU clock frequency cpu_6x4x (MHz) def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False):
#CONFIG_EZYNQ_CLK_CPU_MODE = 6_2_1 # CPU clocks set 6:2:1 (6:3:2:1) or 4:2:1 (4:2:2:1) clk_register_set=self.clk_register_set
clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
#CONFIG_EZYNQ_CLK_FPGA0 = 50.0 # FPGA 0 clock frequency (MHz) # Bypass used PLL-s - stage 1 of PLL setup
#CONFIG_EZYNQ_CLK_FPGA1 = 50.0 # FPGA 1 clock frequency (MHz) self.clocks_rbl_pll_bypass(force=False,warn=False)
#CONFIG_EZYNQ_CLK_FPGA2 = 50.0 # FPGA 2 clock frequency (MHz) _ = clk_register_set.get_register_sets(True,True) # close previous register settings
#CONFIG_EZYNQ_CLK_FPGA3 = 50.0 # FPGA 3 clock frequency (MHz) # Turn on PLL reset and program feedback - stage 2 of PLL setup
self.clocks_rbl_pll_reset_and_fdiv(force=False,warn=False)
#CONFIG_EZYNQ_CLK_FPGA0_SRC = IO # FPGA 0 clock source _ = clk_register_set.get_register_sets(True,True) # close previous register settings
#CONFIG_EZYNQ_CLK_FPGA1_SRC = IO # FPGA 1 clock source # Configure PLL parameters - stage 3 of PLL setup
#CONFIG_EZYNQ_CLK_FPGA2_SRC = IO # FPGA 2 clock source self.clocks_rbl_pll_conf(force=False,warn=False)
#CONFIG_EZYNQ_CLK_FPGA3_SRC = IO # FPGA 3 clock source _ = clk_register_set.get_register_sets(True,True) # close previous register settings
# Release reset of the PLLs (let them start) - stage 4 of PLL setup
############# Normally do not need to be modified ############# self.clocks_rbl_pll_start(force=False,warn=False)
#CONFIG_EZYNQ_CLK_DDR_DCI_MHZ = 10.0 # DDR DCI clock frequency (MHz). Normally 10 Mhz'}, _ = clk_register_set.get_register_sets(True,True) # close previous register settings
#CONFIG_EZYNQ_CLK_DDR2X_MHZ = 355.556 # DDR2X clock frequency (MHz). Does not need to be exactly 2/3 of DDR3X clock'}, # Do after PLL bypass and Reset - stage 5 of clocks setup
#CONFIG_EZYNQ_CLK_DDR_DCI_MHZ= 10.0 # DDR DCI clock frequency (MHz). Normally 10Mhz self.clocks_rbl_program(force=False,warn=False)
#CONFIG_EZYNQ_CLK_SMC_MHZ = 100.0 # Static memory controller clock frequency (MHz). Normally 100 Mhz
#CONFIG_EZYNQ_CLK_QSPI_MHZ = 200.0 # Quad SPI memory controller clock frequency (MHz). Normally 200 Mhz # #Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?
#CONFIG_EZYNQ_CLK_GIGE0_MHZ = 125.0 # GigE 0 Ethernet controller reference clock frequency (MHz). Normally 125 Mhz # _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
#CONFIG_EZYNQ_CLK_GIGE1_MHZ = 125.0 # GigE 1 Ethernet controller reference clock frequency (MHz). Normally 125 Mhz # ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)
#CONFIG_EZYNQ_CLK_SDIO_MHZ = 100.0 # SDIO controller reference clock frequency (MHz). Normally 100 Mhz # _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
#CONFIG_EZYNQ_CLK_UART_MHZ = 25.0 # UART controller reference clock frequency (MHz). Normally 25 Mhz # ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)
#CONFIG_EZYNQ_CLK_SPI_MHZ = 200.0 # SPI controller reference clock frequency (MHz). Normally 200 Mhz # _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
#CONFIG_EZYNQ_CLK_CAN_MHZ = 100.0 # CAN controller reference clock frequency (MHz). Normally 100 Mhz # ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
#CONFIG_EZYNQ_CLK_PCAP_MHZ = 200.0 # PCAP clock frequency (MHz). Normally 200 Mhz # ('enable',1),
#CONFIG_EZYNQ_CLK_TRACE_MHZ = 100.0 # Trace Port clock frequency (MHz). Normally 100 Mhz # ('nref_opt1',0),
#CONFIG_EZYNQ_CLK_ARM_SRC = ARM # ARM CPU clock source (normally ARM PLL) # ('nref_opt2',0),
#CONFIG_EZYNQ_CLK_DDR_SRC = DDR # DDR (DDR2x, DDR3x) clock source (normally DDR PLL) # ('nref_opt4',1),
#CONFIG_EZYNQ_CLK_DCI_SRC = DDR # DDR DCI clock source (normally DDR PLL) # ('pref_opt2',0),
#CONFIG_EZYNQ_CLK_SMC_SRC = IO # Static memory controller clock source (normally IO PLL) # ('update_control',0)),force,warn)
#CONFIG_EZYNQ_CLK_QSPI_SRC = IO # Quad SPI memory controller clock source (normally IO PLL)
#CONFIG_EZYNQ_CLK_GIGE0_SRC = IO # GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO)
#CONFIG_EZYNQ_CLK_GIGE1_SRC = IO # GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO)
#CONFIG_EZYNQ_CLK_SDIO_SRC = IO # SDIO controller clock source (normally IO PLL) #Bypass used PLL-s - stage 1 of PLL setup
#CONFIG_EZYNQ_CLK_UART_SRC = IO # UART controller clock source (normally IO PLL) def clocks_rbl_pll_bypass(self,force=False,warn=False):
#CONFIG_EZYNQ_CLK_SPI_SRC = IO # SPI controller clock source (normally IO PLL) clk_register_set=self.clk_register_set
#CONFIG_EZYNQ_CLK_CAN_SRC = IO # CAN controller clock source (normally IO PLL) if self.verbosity>0 :
#CONFIG_EZYNQ_CLK_PCAP_SRC = IO # PCAP controller clock source (normally IO PLL) print 'pll_fdivs=', self.pll_fdivs
#CONFIG_EZYNQ_CLK_TRACE_SRC = IO # Trace Port clock source (normally IO PLL) if 'DDR' in self.pll_fdivs:
clk_register_set.set_bitfields('ddr_pll_ctrl',( # Bypass override control: 1 - bypassed, 0: if pll_bypass_qual==0: enabled, not bypassed else depends on pin strap
('pll_bypass_qual', 0), # no more reagard for pin strap
('pll_bypass_force', 1)),force,warn)
if 'IO' in self.pll_fdivs:
clk_register_set.set_bitfields('io_pll_ctrl', ( # Bypass override control: 1 - bypassed, 0: if pll_bypass_qual==0: enabled, not bypassed else depends on pin strap
('pll_bypass_qual', 0), # no more reagard for pin strap
##### performance data, final values (overwrite calculated) ##### ('pll_bypass_force', 1)),force,warn)
#CONFIG_EZYNQ_CLK_SPEED_GRADE = 2 # Device speed grade if 'ARM' in self.pll_fdivs:
#CONFIG_EZYNQ_CLK_PLL_MAX_MHZ = 1800.0 # Maximal PLL clock frequency, MHz. Overwrites default for selected speed grade: (Speed grade -1:1600, -2:1800, -3:2000)'}, clk_register_set.set_bitfields('arm_pll_ctrl',( # Bypass override control: 1 - bypassed, 0: if pll_bypass_qual==0: enabled, not bypassed else depends on pin strap
#CONFIG_EZYNQ_CLK_PLL_MIN_MHZ = 780.0 # Minimal PLL clock frequency, all speed grades (MHz)'}, ('pll_bypass_qual', 0), # no more reagard for pin strap
#CONFIG_EZYNQ_CLK_ARM621_MAX_MHZ = 733.0 # Maximal ARM clk_6x4x in 621 mode, MHz. Overwrites default for selected speed grade: (Speed grade -1:667, -2:733, -3:1000)'}, ('pll_bypass_force', 1)),force,warn)
#CONFIG_EZYNQ_CLK_ARM421_MAX_MHZ = 600.0 # Maximal ARM clk_6x4x in 421 mode, MHz. Overwrites default for selected speed grade: (Speed grade -1:533, -2:600, -3:710)'},
#CONFIG_EZYNQ_CLK_DDR_3X_MAX_MHZ = 533.0 # Maximal DDR clk_3x clock frequency (MHz). Overwrites DDR-type/speed grade specific'}, # Turn on PLL reset and program feedback - stage 2 of PLL setup
#CONFIG_EZYNQ_CLK_DDR_2X_MAX_MHZ = 408.0 # Maximal DDR_2X clock frequency (MHz). Overwrites speed grade specific'}, def clocks_rbl_pll_reset_and_fdiv(self,force=False,warn=False):
clk_register_set=self.clk_register_set
##### datasheet data for specific speed grades ##### if 'DDR' in self.pll_fdivs:
#CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ = 1600.0 # Maximal PLL clock frequency for speed grade 1 (MHz)'}, clk_register_set.set_bitfields('ddr_pll_ctrl',( #
#CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ = 1800.0 # Maximal PLL clock frequency for speed grade 2 (MHz)'}, ('pll_fdiv', self.pll_fdivs['DDR']),
#CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ = 2000.0 # Maximal PLL clock frequency for speed grade 3 (MHz)'}, ('pll_reset', 1)),force,warn)
#CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ = 667.0 # Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz'}, if 'IO' in self.pll_fdivs:
#CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ = 733.0 #Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz'}, clk_register_set.set_bitfields('io_pll_ctrl',( #
#CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ =1000.0 #Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz'}, ('pll_fdiv', self.pll_fdivs['IO']),
#CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ = 533.0 # Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz'}, ('pll_reset', 1)),force,warn)
#CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ = 600.0 # Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz'}, if 'ARM' in self.pll_fdivs:
#CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ = 710.0 # Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz'}, clk_register_set.set_bitfields('arm_pll_ctrl',( #
('pll_fdiv', self.pll_fdivs['ARM']),
#CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS = 1066.0 # Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1'}, ('pll_reset', 1)),force,warn)
#CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS = 1066.0 # Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2'},
#CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS = 1333.0 # Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3'}, # Configure PLL parameters - stage 3 of PLL setup
#CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS = 800.0 # Maximal DDR3L, DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades'}, def clocks_rbl_pll_conf(self,force=False,warn=False):
#CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ = 355.0 # Maximal DDR_2X clock frequency (MHz) for speed grade 1'}, clk_register_set=self.clk_register_set
#CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ = 408.0 # Maximal DDR_2X clock frequency (MHz) for speed grade 2'}, if 'DDR' in self.pll_fdivs:
#CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ = 444.0 # Maximal DDR_2X clock frequency (MHz) for speed grade 3'}, ddr_fdiv=self.pll_fdivs['DDR']
clk_register_set.set_bitfields('ddr_pll_cfg',( # DDR PLL Configuration
('lock_cnt', self.pll_pars[ddr_fdiv]['LOCK_CNT']), # Lock status bit delay (in clock cycles)
('pll_cp', self.pll_pars[ddr_fdiv]['PLL_CP']), # PLL charge pump control
('pll_res', self.pll_pars[ddr_fdiv]['PLL_RES']), # PLL loop filter resistor control
),force,warn)
if 'IO' in self.pll_fdivs:
io_fdiv=self.pll_fdivs['IO']
clk_register_set.set_bitfields('io_pll_cfg',( # IO PLL Configuration
('lock_cnt', self.pll_pars[io_fdiv]['LOCK_CNT']), # Lock status bit delay (in clock cycles)
('pll_cp', self.pll_pars[io_fdiv]['PLL_CP']), # PLL charge pump control
('pll_res', self.pll_pars[io_fdiv]['PLL_RES']), # PLL loop filter resistor control
),force,warn)
if 'ARM' in self.pll_fdivs:
arm_fdiv=self.pll_fdivs['ARM']
clk_register_set.set_bitfields('arm_pll_cfg',( # ARM PLL Configuration
('lock_cnt', self.pll_pars[arm_fdiv]['LOCK_CNT']), # Lock status bit delay (in clock cycles)
('pll_cp', self.pll_pars[arm_fdiv]['PLL_CP']), # PLL charge pump control
('pll_res', self.pll_pars[arm_fdiv]['PLL_RES']), # PLL loop filter resistor control
),force,warn)
# Release reset of the PLLs (let them start) - stage 4 of PLL setup
def clocks_rbl_pll_start(self,force=False,warn=False):
clk_register_set=self.clk_register_set
if 'DDR' in self.pll_fdivs:
clk_register_set.set_bitfields('ddr_pll_ctrl',(('pll_reset', 0)),force,warn)
if 'IO' in self.pll_fdivs:
clk_register_set.set_bitfields('io_pll_ctrl', (('pll_reset', 0)),force,warn)
if 'ARM' in self.pll_fdivs:
clk_register_set.set_bitfields('arm_pll_ctrl',(('pll_reset', 0)),force,warn)
# Do after PLL bypass and Reset - stage 5 of clocks setup
def clocks_rbl_program(self,force=False,warn=False):
clk_register_set=self.clk_register_set
# PLLs are now bypassed and reset, now program
# reg arm_clk_ctrl, offs=0x120 dflt:0x1f000400 actual: 0x1f000200
cpu_peri_clkact = 1
cpu_1x_clkact= 1
cpu_2x_clkact= 1
cpu_3x2x_clkact= 1
cpu_6x4x_clkact= 1
try:
cpu_divisor= self.iface_divs['ARM']['DIV'] # Should be set - 0x2
except:
raise Exception ('Unknown ARM clock divisor - should be set by now')
if self.iface_divs['ARM']['PLL']=='ARM':
cpu_srcsel= 0
elif self.iface_divs['ARM']['PLL']=='DDR':
cpu_srcsel= 2
else: # if self.iface_divs['ARM']['PLL']=='IO':
cpu_srcsel= 3
clk_register_set.set_bitfields('arm_clk_ctrl',( # CPU clock control
# ('reserved1', 0), #
('cpu_peri_clkact', cpu_peri_clkact), # Peripheral clock active (0 - disabled)
('cpu_1x_clkact', cpu_1x_clkact), # CPU-1x clock active (0 - disabled)
('cpu_2x_clkact', cpu_2x_clkact), # CPU-2x clock active (0 - disabled)
('cpu_3x2x_clkact', cpu_3x2x_clkact), # CPU-3x2x clock active (0 - disabled)
('cpu_6x4x_clkact', cpu_6x4x_clkact), # CPU-6x4x clock active (0 - disabled)
# ('reserved2', 0), #
('divisor', cpu_divisor), # Frequency divisor for the CPU clock source. If PLL is NOT bypassed values 1 and 3 are invalid #2
# ('reserved3', 0), #
('srcsel', cpu_srcsel), # CPU clock source: 0,1 - ARM PLL, 2 - DDR PLL, 3 - IO PLL, This filed is reset by POR only #0
# ('reserved4', 0), #
),force,warn)
# reg ddr_clk_ctrl, offs=0x124 dflt:0x18400003 actual: 0xc200003
try:
ddr_2x_clk_divisor= self.iface_divs['DDR2X']['DIV'] # 0x3
ddr_2x_clkact = 1
except: # not defined
ddr_2x_clk_divisor= 0
ddr_2x_clkact = 0
try:
ddr_3x_clk_divisor= self.iface_divs['DDR']['DIV'] # 0x2
ddr_3x_clkact = 0x1
except: # not defined
ddr_3x_clk_divisor= 0
ddr_3x_clkact = 0
clk_register_set.set_bitfields('ddr_clk_ctrl',( # DDR_3x (including PHY) and DDR_2X clock control
('ddr_2x_clk_divisor', ddr_2x_clk_divisor), # 0x3 Frequency divisor for ddr_2x clk
('ddr_3x_clk_divisor', ddr_3x_clk_divisor), # 0x2 Frequency divisor for ddr_3x clk
# ('reserved1', 0), # reserved
('ddr_2x_clkact', ddr_2x_clkact), # 0x1 1 - ddr_2x clk enabled (0 - disabled)
('ddr_3x_clkact', ddr_3x_clkact), # 0x1 1 - ddr_3x clk enabled (0 - disabled)
),force,warn)
# reg dci_clk_ctrl, offs=0x128 dflt:0x18400003 actual: 0x302301
try:
dci_divisor1 = self.iface_divs['DDR_DCI']['DIV2'] # 0x3
dci_divisor0 = self.iface_divs['DDR_DCI']['DIV'] # 0x23
dci_clkact = 1 #0x1
except: # not defined
dci_divisor1 = 0
dci_divisor0 = 0
dci_clkact = 0
clk_register_set.set_bitfields('dci_clk_ctrl',( # DDR DCI clock control
# ('reserved1', 0), #
('divisor1', dci_divisor1), # 0x3 Frequency divisor, second stage
# ('reserved2', 0), #
('divisor0', dci_divisor0), # 0x23 Frequency divisor, first stage
# ('reserved3', 0), #
('clkact', dci_clkact), # 0x1 1 - dci clock enabled (0 - disabled)
),force,warn)
# reg aper_clk_ctrl, offs=0x12c dflt:0x01ffcccd actual: 0x01ec044d (set after peripherals - does it really need so?
smc_cpu_1x_clkact = 'SMC' in self.iface_divs # 0x1
lqspi_cpu_1x_clkact = 'QSPI' in self.iface_divs # 0x1
gpio_cpu_1x_clkact = 1 # 0x1
uart1_cpu_1x_clkact = 'UART1' in self.iface_divs # 0x1
uart0_cpu_1x_clkact = 'UART0' in self.iface_divs # 0x1
i2c1_cpu_1x_clkact = 'I2C1' in self.iface_divs # 0x1
i2c0_cpu_1x_clkact = 'I2C0' in self.iface_divs # 0x1
can1_cpu_1x_clkact = 'CAN1' in self.iface_divs # 0x1
can0_cpu_1x_clkact = 'CAN0' in self.iface_divs # 0x1
spi1_cpu_1x_clkact = 'SPI1' in self.iface_divs # 0x1
spi0_cpu_1x_clkact = 'SPI0' in self.iface_divs # 0x1
sdi1_cpu_1x_clkact = 'SDI1' in self.iface_divs # 0x1
sdi0_cpu_1x_clkact = 'SDI0' in self.iface_divs # 0x1
gem1_cpu_1x_clkact = 'GIGE1' in self.iface_divs # 0x1
gem0_cpu_1x_clkact = 'GIGE0' in self.iface_divs # 0x1
usb1_cpu_1x_clkact = 'USB1' in self.iface_divs # 0x1
usb0_cpu_1x_clkact = 'USB1' in self.iface_divs # 0x1
dma_cpu_2x_clkact = 1 # 0x1
clk_register_set.set_bitfields('aper_clk_ctrl',( # AMBA peripherals clock control
# ('reserved1', 0), #
('smc_cpu_1x_clkact', smc_cpu_1x_clkact), # 0x1 SMC AMBA clock control (1- enabled, 0- disabled)
('lqspi_cpu_1x_clkact', lqspi_cpu_1x_clkact), # 0x1 QSPI AMBA clock control (1- enabled, 0- disabled)
('gpio_cpu_1x_clkact', gpio_cpu_1x_clkact), # 0x1 GPIO AMBA clock control (1- enabled, 0- disabled)
('uart1_cpu_1x_clkact', uart1_cpu_1x_clkact), # 0x1 UART1 AMBA clock control (1- enabled, 0- disabled)
('uart0_cpu_1x_clkact', uart0_cpu_1x_clkact), # 0x1 UART0 AMBA clock control (1- enabled, 0- disabled)
('i2c1_cpu_1x_clkact', i2c1_cpu_1x_clkact), # 0x1 I2C1 AMBA clock control (1- enabled, 0- disabled)
('i2c0_cpu_1x_clkact', i2c0_cpu_1x_clkact), # 0x1 I2C0 AMBA clock control (1- enabled, 0- disabled)
('can1_cpu_1x_clkact', can1_cpu_1x_clkact), # 0x1 CAN1 AMBA clock control (1- enabled, 0- disabled)
('can0_cpu_1x_clkact', can0_cpu_1x_clkact), # 0x1 CAN0 AMBA clock control (1- enabled, 0- disabled)
('spi1_cpu_1x_clkact', spi1_cpu_1x_clkact), # 0x1 SPI1 AMBA clock control (1- enabled, 0- disabled)
('spi0_cpu_1x_clkact', spi0_cpu_1x_clkact), # 0x1 SPI0 AMBA clock control (1- enabled, 0- disabled)
# ('reserved2', 0), #
# ('reserved3', 0), #
('sdi1_cpu_1x_clkact', sdi1_cpu_1x_clkact), # 0x1 SDI1 AMBA clock control (1- enabled, 0- disabled)
('sdi0_cpu_1x_clkact', sdi0_cpu_1x_clkact), # 0x1 SDI0 AMBA clock control (1- enabled, 0- disabled)
('reserved4', 0), #
('reserved5', 0), #
('gem1_cpu_1x_clkact', gem1_cpu_1x_clkact), # 0x1 Gigabit Ethernet 1 AMBA clock control (1- enabled, 0- disabled)
('gem0_cpu_1x_clkact', gem0_cpu_1x_clkact), # 0x1 Gigabit Ethernet 0 AMBA clock control (1- enabled, 0- disabled)
# ('reserved6', 0), #
# ('reserved7', 0), #
('usb1_cpu_1x_clkact', usb1_cpu_1x_clkact), # 0x1 USB1 AMBA clock control (1- enabled, 0- disabled)
('usb0_cpu_1x_clkact', usb0_cpu_1x_clkact), # 0x1 USB0 AMBA clock control (1- enabled, 0- disabled)
# ('reserved2', 0), #
('dma_cpu_2x_clkact', dma_cpu_2x_clkact), # 0x1 DMA controller AMBA clock control (1- enabled, 0- disabled)
),force,warn)
if 'USB0' in self.iface_divs:
# reg usb0_clk_ctrl, offs=0x130 dflt:0x00101941 actual: never set
usb0_srcsel= 4 # Only possible
clk_register_set.set_bitfields('usb0_clk_ctrl',( # USB 0 ULPI clock control
('reserved1', 0),
('reserved2', 0x1),
('reserved3', 0),
('reserved4', 0x19),
('reserved5', 0),
('srcsel', usb0_srcsel),
('reserved6', 0),
('reserved7', 1),
),force,warn)
if 'USB1' in self.iface_divs:
# reg usb1_clk_ctrl, offs=0x134 dflt:0x00101941 actual: never set
usb1_srcsel= 4 # Only possible
clk_register_set.set_bitfields('usb0_clk_ctrl',( # USB 1 ULPI clock control
# ('reserved1', 0),
# ('reserved2', 0x1),
# ('reserved3', 0),
# ('reserved4', 0x19),
# ('reserved5', 0),
('srcsel', usb1_srcsel),
# ('reserved6', 0),
# ('reserved7', 1),
),force,warn)
# reg gem0_rclk_ctrl, offs=0x138 dflt:0x1 actual: 0x1
try:
gem0_rclk_srcsel=self.iface_divs['GIGE0']['SOURCE']=='EMIO'
gem0_rclk_clkact=1
except:
gem0_rclk_srcsel=0
if 'GIGE0' in self.iface_divs:
gem0_rclk_clkact=1
else:
gem0_rclk_clkact=0
clk_register_set.set_bitfields('gem0_rclk_ctrl',( # Gigabit Ethernet 0 RX clock and RX signals select
# ('reserved1', 0), #
('srcsel', gem0_rclk_srcsel), #
# ('reserved2', 0), #
('clkact', gem0_rclk_clkact), #
),force,warn)
# reg gem1_rclk_ctrl, offs=0x13c dflt:0x1 actual: 0x1
try:
gem1_rclk_srcsel=self.iface_divs['GIGE1']['SOURCE']=='EMIO'
gem1_rclk_clkact=1
except:
gem1_rclk_srcsel=0
if 'GIGE1' in self.iface_divs:
gem1_rclk_clkact=1
else:
gem1_rclk_clkact=0
clk_register_set.set_bitfields('gem1_rclk_ctrl',( # Gigabit Ethernet 0 RX clock and RX signals select
# ('reserved1', 0), #
('srcsel', gem1_rclk_srcsel), #
# ('reserved2', 0), #
('clkact', gem1_rclk_clkact), #
),force,warn)
# reg gem0_clk_ctrl, offs=0x140 dflt:0x3c01 actual: 0x100801
# set frequency divisors if specified, otherwise - set them to "1"
try:
gem0_divisor=self.iface_divs['GIGE0']['DIV']
except:
gem0_divisor=1
try:
gem0_divisor1=self.iface_divs['GIGE0']['DIV2']
except:
gem0_divisor1=1
try:
if self.iface_divs['GIGE0']['SOURCE']=='EMIO': # may cause exception
gem0_srcsel= 4
gem0_clkact=1
except: # GIGE0 or GIGE0 source are not specified
if 'GIGE0' in self.iface_divs:
if self.iface_divs['GIGE0']['PLL']=='ARM':
gem0_srcsel= 2
elif self.iface_divs['GIGE0']['PLL']=='DDR':
gem0_srcsel= 3
else: # if self.iface_divs['GIGE0']['PLL']=='IO':
gem0_srcsel= 0
gem0_clkact=1
else:
gem0_srcsel= 0
gem0_clkact=0
clk_register_set.set_bitfields('gem0_clk_ctrl',( # Gigabit Ethernet 0 Reference clock control
# ('reserved1', 0), #
('divisor1', gem0_divisor1), # 0x1
# ('reserved2', 0), #
('divisor', gem0_divisor), # 0x8
# ('reserved3', 0), #
('srcsel', gem0_srcsel), # 0x0
# ('reserved4', 0), #
('clkact', gem0_clkact), # 0x1
),force,warn)
# reg gem1_clk_ctrl, offs=0x144 dflt:0x3c01 actual: never set
# set frequency divisors if specified, otherwise - set them to "1"
try:
gem1_divisor=self.iface_divs['GIGE1']['DIV']
except:
gem1_divisor=1
try:
gem1_divisor1=self.iface_divs['GIGE1']['DIV2']
except:
gem1_divisor1=1
try:
if self.iface_divs['GIGE1']['SOURCE']=='EMIO': # may cause exception
gem1_srcsel= 4
gem1_clkact=1
except: # GIGE1 or GIGE1 source are not specified
if 'GIGE1' in self.iface_divs:
if self.iface_divs['GIGE1']['PLL']=='ARM':
gem1_srcsel= 2
elif self.iface_divs['GIGE1']['PLL']=='DDR':
gem1_srcsel= 3
else: # if self.iface_divs['GIGE1']['PLL']=='IO':
gem1_srcsel= 0
gem1_clkact=1
else:
gem1_srcsel= 0
gem1_clkact=0
clk_register_set.set_bitfields('gem1_clk_ctrl',( # Gigabit Ethernet 1 Reference clock control
# ('reserved1', 0), #
('divisor1', gem1_divisor1), # 0x1
# ('reserved2', 0), #
('divisor', gem1_divisor), # 0x8
# ('reserved3', 0), #
('srcsel', gem1_srcsel), # 0x0
# ('reserved4', 0), #
('clkact', gem1_clkact), # 0x1
),force,warn)
# Is it OK to modify it now (in RBL) - maybe NAND is being used ?
# reg smc_clk_ctrl, offs=0x148 dflt:0x3c21 actual: Never modified
if 'SMC' in self.iface_divs:
if self.iface_divs['SMC']['PLL']=='ARM':
smc_srcsel= 2
elif self.iface_divs['SMC']['PLL']=='DDR':
smc_srcsel= 3
else: # if self.iface_divs['SMC']['PLL']=='IO':
smc_srcsel= 0
smc_divisor=self.iface_divs['SMC']['DIV']
smc_clkact=1
else:
smc_divisor= 1
smc_srcsel= 0
smc_clkact=0
clk_register_set.set_bitfields('smc_clk_ctrl',( # SMC Reference clock control
('reserved1', 0), #
('divisor', smc_divisor),# Frequency divisor
('reserved2', 0), #
('srcsel', smc_srcsel), # Source select: 0,1-IO PLL, 2 - ARM PLL, 3 - DDR PLL
('reserved3', 0), #
('clkact', smc_clkact), # SMC reference clock: 1 - enabled (0 - disabled)
),force,warn)
# Is it OK to modify it now (in RBL) - maybe QSPI is being used ?
# reg lqspi_clk_ctrl, offs=0x14c dflt:0x2821 actual: 0x721
if 'QSPI' in self.iface_divs:
if self.iface_divs['QSPI']['PLL']=='ARM':
qspi_srcsel= 2
elif self.iface_divs['QSPI']['PLL']=='DDR':
qspi_srcsel= 3
else: # if self.iface_divs['QSPI']['PLL']=='IO':
qspi_srcsel= 0
qspi_divisor=self.iface_divs['QSPI']['DIV']
qspi_clkact=1
else:
qspi_divisor= 1
qspi_srcsel= 0
qspi_clkact=0
clk_register_set.set_bitfields('lqspi_clk_ctrl',( # Quad SPI Reference clock control
# ('reserved1', 0), #
('divisor', qspi_divisor), # 0x7 Frequency divisor
# ('reserved2', 0), #
('srcsel', qspi_srcsel), # 0x2 Source select: 0,1-IO PLL, 2 - ARM PLL, 3 - DDR PLL
# ('reserved3', 0), #
('clkact', qspi_clkact), # 0x1 Quad SPI reference clock: 1 - enabled (0 - disabled)
),force,warn)
# Is it OK to modify it now (in RBL) - if SDIO is being used ?
# reg sdio_clk_ctrl, offs=0x150 dflt:0x1e03 actual: 0x801
if 'SDIO' in self.iface_divs:
if self.iface_divs['SDIO']['PLL']=='ARM':
sdio_srcsel= 2
elif self.iface_divs['SDIO']['PLL']=='DDR':
sdio_srcsel= 3
else: # if self.iface_divs['SDIO']['PLL']=='IO':
sdio_srcsel= 0
sdio_divisor=self.iface_divs['SDIO']['DIV']
sdio_clkact1='SDIO1' in self.iface_divs
sdio_clkact0='SDIO0' in self.iface_divs
else:
sdio_divisor= 1
sdio_srcsel = 0
sdio_clkact1 = 0
sdio_clkact0 = 0
clk_register_set.set_bitfields('sdio_clk_ctrl',( # SDIO 0,1 Reference clock control
# ('reserved1', 0), #
('divisor', sdio_divisor), # 0x8 Frequency divisor
# ('reserved2', 0), #
('srcsel', sdio_srcsel), # 0x0 Source select: 0,1-IO PLL, 2 - ARM PLL, 3 - DDR PLL
# ('reserved3', 0), #
('clkact1', sdio_clkact1), # 0x0 SDIO 1 reference clock: 1 - enabled (0 - disabled)
('clkact0', sdio_clkact0), # 0x1 SDIO 0 reference clock: 1 - enabled (0 - disabled)
),force,warn)
# reg uart_clk_ctrl, offs=0x154 dflt:0x3f03 actual: 0xa02
if 'UART' in self.iface_divs:
if self.iface_divs['UART']['PLL']=='ARM':
uart_srcsel= 2
elif self.iface_divs['UART']['PLL']=='DDR':
uart_srcsel= 3
else: # if self.iface_divs['UART']['PLL']=='IO':
uart_srcsel= 0
uart_divisor=self.iface_divs['UART']['DIV']
uart_clkact1='UART1' in self.iface_divs
uart_clkact0='UART0' in self.iface_divs
else:
uart_divisor= 1
uart_srcsel = 0
uart_clkact1 = 0
uart_clkact0 = 0
clk_register_set.set_bitfields('uart_clk_ctrl',( # UART 0,1 Reference clock control
# ('reserved1', 0), #
('divisor', uart_divisor), # 0xa Frequency divisor
# ('reserved2', 0), #
('srcsel', uart_srcsel), # 0x0 Source select: 0,1-IO PLL, 2 - ARM PLL, 3 - DDR PLL
# ('reserved3', 0), #
('clkact1', uart_clkact1), # 0x1 UART 1 reference clock: 1 - enabled (0 - disabled)
('clkact0', uart_clkact0), # 0x0 UART 0 reference clock: 1 - enabled (0 - disabled)
),force,warn)
#
# 'spi_clk_ctrl': {'OFFS': 0x158,'DFLT':0x3f03,'RW':'RW', # Never set
# 'COMMENTS':'SPI 0,1 Reference clock control',
# 'FIELDS':{
# reg spi_clk_ctrl, offs=0x158 dflt:0x3f03 actual: Never set
if 'SPI' in self.iface_divs:
if self.iface_divs['SPI']['PLL']=='ARM':
spi_srcsel= 2
elif self.iface_divs['SPI']['PLL']=='DDR':
spi_srcsel= 3
else: # if self.iface_divs['SPI']['PLL']=='IO':
spi_srcsel= 0
spi_divisor=self.iface_divs['SPI']['DIV']
spi_clkact1='SPI1' in self.iface_divs
spi_clkact0='SPI0' in self.iface_divs
else:
spi_divisor= 1
spi_srcsel = 0
spi_clkact1 = 0
spi_clkact0 = 0
clk_register_set.set_bitfields('spi_clk_ctrl',( # SPI 0,1 Reference clock control
# ('reserved1', 0), #
('divisor', spi_divisor), # Frequency divisor
# ('reserved2', 0), #
('srcsel', spi_srcsel), # Source select: 0,1-IO PLL, 2 - ARM PLL, 3 - DDR PLL
# ('reserved3', 0), #
('clkact1', spi_clkact1), # SPI 1 reference clock: 1 - enabled (0 - disabled)
('clkact0', spi_clkact0), # SPI 0 reference clock: 1 - enabled (0 - disabled)
),force,warn)
# reg can_clk_ctrl, offs=0x15c dflt:0x501903 actual: Never set
if 'CAN' in self.iface_divs:
if self.iface_divs['CAN']['PLL']=='ARM':
can_srcsel= 2
elif self.iface_divs['CAN']['PLL']=='DDR':
can_srcsel= 3
else: # if self.iface_divs['CAN']['PLL']=='IO':
can_srcsel= 0
can_divisor1=self.iface_divs['CAN']['DIV2']
can_divisor= self.iface_divs['CAN']['DIV']
can_clkact1='CAN1' in self.iface_divs
can_clkact0='CAN0' in self.iface_divs
else:
can_divisor1= 1
can_divisor= 1
can_srcsel = 0
can_clkact1 = 0
can_clkact0 = 0
clk_register_set.set_bitfields('can_clk_ctrl',( # CAN 0,1 Reference clock control
# ('reserved1', 0), #
('divisor1',can_divisor1), # Frequency divisor, second stage
# ('reserved2', 0), #
('divisor', can_divisor), # Frequency divisor
# ('reserved3', 0), #
('srcsel', can_srcsel), # Source select: 0,1-IO PLL, 2 - ARM PLL, 3 - DDR PLL
# ('reserved4', 0), #
('clkact1', can_clkact1), # CAN 1 reference clock: 1 - enabled (0 - disabled)
('clkact0', can_clkact0), # can 0 reference clock: 1 - enabled (0 - disabled)
),force,warn)
# print 'self.used_mio_interfaces=',self.used_mio_interfaces
for mio_iface in self.used_mio_interfaces:
if (mio_iface['NAME']=='CAN_ECLK') and (mio_iface['CHANNEL']==0):
can0_mux= mio_iface['PIN']
can0_ref_sel=1
break
else:
can0_mux= 0
can0_ref_sel=0
for mio_iface in self.used_mio_interfaces:
if (mio_iface['NAME']=='CAN_ECLK') and (mio_iface['CHANNEL']==1):
can1_mux= mio_iface['PIN']
can1_ref_sel=1
break
else:
can1_mux= 0
can1_ref_sel=0
# reg can_mioclk_ctrl, offs=0x160 dflt:0x0 actual: Never set
clk_register_set.set_bitfields('can_mioclk_ctrl',( # CAN MIO clock control
# ('reserved1', 0), #
('can1_ref_sel', can1_ref_sel), # CAN1 reference clock selection: 0: from internal PLL, 1 - from MIO based on can1_mux selection
('can1_mux', can1_mux), # CAN1 MIO pin selection (valid: 0..53)
# ('reserved2', 0), #
('can0_ref_sel', can0_ref_sel), # CAN0 reference clock selection: 0: from internal PLL, 1 - from MIO based on can0_mux selection
('can0_mux', can0_mux), # CAN0 MIO pin selection (valid: 0..53)
),force,warn)
# reg dbg_clk_ctrl, offs=0x164 dflt:0xf03 actual: ever set
if 'TRACE' in self.iface_divs:
try:
dbg_divisor=self.iface_divs['TRACE']['DIV']
except:
dbg_divisor=1
try:
if self.iface_divs['TRACE']['SOURCE']=='EMIO': # may cause exception
dbg_srcsel= 4
dbg_clkact_trc=1
except:
if self.iface_divs['TRACE']['PLL']=='ARM':
dbg_srcsel= 2
elif self.iface_divs['TRACE']['PLL']=='DDR':
dbg_srcsel= 3
else: # if self.iface_divs['TRACE']['PLL']=='IO':
dbg_srcsel= 0
dbg_clkact_trc=1
else:
dbg_divisor=0xf # default
dbg_srcsel= 0 # rurn off
dbg_cpu_1x_clkact = 1 # always (is it the same as used for otgher peripherals and should be on?)
clk_register_set.set_bitfields('dbg_clk_ctrl',( # SoC debug clock control
# ('reserved1', 0), #
('divisor', dbg_divisor), # Frequency divisor
# ('reserved2', 0), #
('srcsel', dbg_srcsel), # Source select: 0,1-IO PLL, 2 - ARM PLL, 3 - DDR PLL, 4..7 - EMIO trace clock
# ('reserved3', 0), #
('cpu_1x_clkact', dbg_cpu_1x_clkact), # CPU 1x clock: 1 - enabled (0 - disabled)
('clkact_trc', dbg_clkact_trc), # Debug trace clock: 1 - enabled (0 - disabled)
),force,warn)
# reg pcap_clk_ctrl, offs=0x168 dflt:0xf01 actual: 0x501
if 'PCAP' in self.iface_divs:
try:
pcap_divisor=self.iface_divs['PCAP']['DIV']
except:
pcap_divisor=1
if self.iface_divs['PCAP']['PLL']=='ARM':
pcap_srcsel= 2
elif self.iface_divs['PCAP']['PLL']=='DDR':
pcap_srcsel= 3
else: # if self.iface_divs['PCAP']['PLL']=='IO':
pcap_srcsel= 0
pcap_clkact=1
else:
pcap_srcsel= 0
pcap_divisor=5 # default
pcap_clkact=0
clk_register_set.set_bitfields('pcap_clk_ctrl',( # PCAP clock control
# ('reserved1', 0), #
('divisor', pcap_divisor), # 0x5 Frequency divisor
# ('reserved2', 0), #
('srcsel', pcap_srcsel), # Source select: 0,1-IO PLL, 2 - ARM PLL, 3 - DDR PLL
# ('reserved3', 0), #
('clkact', pcap_clkact), # PCAP clock: 1 - enabled (0 - disabled)
),force,warn)
# reg topsw_clk_ctrl, offs=0x16c dflt:0 actual: Never set
clk_dis= 0 # Not disabled (used to put into sleep mode)
clk_register_set.set_bitfields('topsw_clk_ctrl',( # Central interconnect clock control
# ('reserved1', 0), #
('clk_dis', clk_dis), # Central interconnect clock DISABLE: 0 - enabled (1 - disabled)
),force,warn)
# reg fpga0_clk_ctrl, offs=0x170 dflt:0x101800 actual: 0x101400
if 'FPGA0' in self.iface_divs:
try:
fpga0_divisor0=self.iface_divs['FPGA0']['DIV']
except:
fpga0_divisor0=1
try:
fpga0_divisor1=self.iface_divs['FPGA0']['DIV2']
except:
fpga0_divisor1=1
if self.iface_divs['FPGA0']['PLL']=='ARM':
fpga0_srcsel= 2
elif self.iface_divs['FPGA0']['PLL']=='DDR':
fpga0_srcsel= 3
else: # if self.iface_divs['FPGA0']['PLL']=='IO':
fpga0_srcsel= 0
else:
fpga0_srcsel= 0
fpga0_divisor1=0x1 # default
fpga0_divisor0=0x18 # default
clk_register_set.set_bitfields('fpga0_clk_ctrl',( # PL clock 0 output control
# ('reserved1', 0), #
('divisor1', fpga0_divisor1), # 0x1
# ('reserved2', 0), #
('divisor0', fpga0_divisor0), # 0x18
# ('reserved3', 0), #
('srcsel', fpga0_srcsel), # 0x0
# ('reserved4', 0), #
),force,warn)
# reg fpga1_clk_ctrl, offs=0x180 dflt:0x101800 actual: 0x101400
if 'FPGA1' in self.iface_divs:
try:
fpga1_divisor0=self.iface_divs['FPGA1']['DIV']
except:
fpga1_divisor0=1
try:
fpga1_divisor1=self.iface_divs['FPGA1']['DIV2']
except:
fpga1_divisor1=1
if self.iface_divs['FPGA1']['PLL']=='ARM':
fpga1_srcsel= 2
elif self.iface_divs['FPGA1']['PLL']=='DDR':
fpga1_srcsel= 3
else: # if self.iface_divs['FPGA1']['PLL']=='IO':
fpga1_srcsel= 0
else:
fpga1_srcsel= 0
fpga1_divisor1=0x1 # default
fpga1_divisor0=0x18 # default
clk_register_set.set_bitfields('fpga1_clk_ctrl',( # PL clock 0 output control
# ('reserved1', 0), #
('divisor1', fpga1_divisor1), # 0x1
# ('reserved2', 0), #
('divisor0', fpga1_divisor0), # 0x18
# ('reserved3', 0), #
('srcsel', fpga1_srcsel), # 0x0
# ('reserved4', 0), #
),force,warn)
# reg fpga2_clk_ctrl, offs=0x190 dflt:0x101800 actual: 0x101400
if 'FPGA2' in self.iface_divs:
try:
fpga2_divisor0=self.iface_divs['FPGA2']['DIV']
except:
fpga2_divisor0=1
try:
fpga2_divisor1=self.iface_divs['FPGA2']['DIV2']
except:
fpga2_divisor1=1
if self.iface_divs['FPGA2']['PLL']=='ARM':
fpga2_srcsel= 2
elif self.iface_divs['FPGA2']['PLL']=='DDR':
fpga2_srcsel= 3
else: # if self.iface_divs['FPGA2']['PLL']=='IO':
fpga2_srcsel= 0
else:
fpga2_srcsel= 0
fpga2_divisor1=0x1 # default
fpga2_divisor0=0x18 # default
clk_register_set.set_bitfields('fpga2_clk_ctrl',( # PL clock 0 output control
# ('reserved1', 0), #
('divisor1', fpga2_divisor1), # 0x1
# ('reserved2', 0), #
('divisor0', fpga2_divisor0), # 0x18
# ('reserved3', 0), #
('srcsel', fpga2_srcsel), # 0x0
# ('reserved4', 0), #
),force,warn)
# reg fpga3_clk_ctrl, offs=0x1a0 dflt:0x101800 actual: 0x101400
if 'FPGA3' in self.iface_divs:
try:
fpga3_divisor0=self.iface_divs['FPGA3']['DIV']
except:
fpga3_divisor0=1
try:
fpga3_divisor1=self.iface_divs['FPGA3']['DIV2']
except:
fpga3_divisor1=1
if self.iface_divs['FPGA3']['PLL']=='ARM':
fpga3_srcsel= 2
elif self.iface_divs['FPGA3']['PLL']=='DDR':
fpga3_srcsel= 3
else: # if self.iface_divs['FPGA3']['PLL']=='IO':
fpga3_srcsel= 0
else:
fpga3_srcsel= 0
fpga3_divisor1=0x1 # default
fpga3_divisor0=0x18 # default
clk_register_set.set_bitfields('fpga3_clk_ctrl',( # PL clock 0 output control
# ('reserved1', 0), #
('divisor1', fpga3_divisor1), # 0x1
# ('reserved2', 0), #
('divisor0', fpga3_divisor0), # 0x18
# ('reserved3', 0), #
('srcsel', fpga3_srcsel), # 0x0
# ('reserved4', 0), #
),force,warn)
# No FPGAx Throttle control here
# reg clk_621_true, offs=0x1c4 dflt:0x1 actual: 0x1
clk_register_set.set_bitfields('clk_621_true',( # PU clock ratio mode select
# ('reserved', 0), #
('clk_621_true', self.is621)),force,warn) # 0x1 Select the CPU clock ratio: 0- 4:2:1, 1 - 6:2;1. No access to OCM when this value changes
ezynq_clkcfg_defs.py
View file @ e368919b
...@@ -77,14 +77,14 @@ CLK_CFG_DEFS=[ ...@@ -77,14 +77,14 @@ CLK_CFG_DEFS=[
{'NAME':'ARM_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_ARM_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'ARM', {'NAME':'ARM_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_ARM_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'ARM',
'DESCRIPTION':'ARM CPU clock source (normally ARM PLL)'}, 'DESCRIPTION':'ARM CPU clock source (normally ARM PLL)'},
{'NAME':'DDR_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_DDR_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'DDR', {'NAME':'DDR_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_DDR_SRC','TYPE':('DDR',),'MANDATORY':False,'DERIVED':False,'DEFAULT':'DDR',
'DESCRIPTION':'DDR (DDR2x, DDR3x) clock source (normally DDR PLL)'}, 'DESCRIPTION':'DDR (DDR2x, DDR3x) clock source (Only valid DDR PLL)'},
{'NAME':'DDR_DCI_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_DDR_DCI_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'DDR', {'NAME':'DDR_DCI_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_DDR_DCI_SRC','TYPE':('DDR',),'MANDATORY':False,'DERIVED':False,'DEFAULT':'DDR',
'DESCRIPTION':'DDR DCI clock source (normally DDR PLL)'}, 'DESCRIPTION':'DDR DCI clock source (only valid DDR PLL)'},
{'NAME':'SMC_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_SMC_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO', {'NAME':'SMC_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_SMC_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',
'DESCRIPTION':'Static memory controller clock source (normally IO PLL)'}, 'DESCRIPTION':'Static memory controller clock source (normally IO PLL)'},
{'NAME':'QSPI_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_QSPI_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO', {'NAME':'QSPI_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_QSPI_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'ARM',
'DESCRIPTION':'Quad SPI memory controller clock source (normally IO PLL)'}, 'DESCRIPTION':'Quad SPI memory controller clock source (normally ARM PLL)'},
{'NAME':'GIGE0_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_GIGE0_SRC','TYPE':('ARM','DDR','IO','EMIO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO', {'NAME':'GIGE0_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_GIGE0_SRC','TYPE':('ARM','DDR','IO','EMIO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',
'DESCRIPTION':'GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO)'}, 'DESCRIPTION':'GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO)'},
{'NAME':'GIGE1_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_GIGE1_SRC','TYPE':('ARM','DDR','IO','EMIO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO', {'NAME':'GIGE1_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_GIGE1_SRC','TYPE':('ARM','DDR','IO','EMIO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',
...@@ -99,7 +99,7 @@ CLK_CFG_DEFS=[ ...@@ -99,7 +99,7 @@ CLK_CFG_DEFS=[
'DESCRIPTION':'CAN controller clock source (normally IO PLL)'}, 'DESCRIPTION':'CAN controller clock source (normally IO PLL)'},
{'NAME':'PCAP_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_PCAP_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO', {'NAME':'PCAP_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_PCAP_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',
'DESCRIPTION':'PCAP controller clock source (normally IO PLL)'}, 'DESCRIPTION':'PCAP controller clock source (normally IO PLL)'},
{'NAME':'TRACE_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_TRACE_SRC','TYPE':('ARM','DDR','IO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO', {'NAME':'TRACE_SRC', 'CONF_NAME':'CONFIG_EZYNQ_CLK_TRACE_SRC','TYPE':('ARM','DDR','IO','EMIO'),'MANDATORY':False,'DERIVED':False,'DEFAULT':'IO',
'DESCRIPTION':'Trace Port clock source (normally IO PLL)'}, 'DESCRIPTION':'Trace Port clock source (normally IO PLL)'},
# performance data, final values (overwrites calculated) # performance data, final values (overwrites calculated)
...@@ -191,7 +191,7 @@ CLK_CFG_DEFS=[ ...@@ -191,7 +191,7 @@ CLK_CFG_DEFS=[
#CONFIG_EZYNQ_CLK_DDR_SRC = DDR # DDR (DDR2x, DDR3x) clock source (normally DDR PLL) #CONFIG_EZYNQ_CLK_DDR_SRC = DDR # DDR (DDR2x, DDR3x) clock source (normally DDR PLL)
#CONFIG_EZYNQ_CLK_DDR_DCI_SRC = DDR # DDR DCI clock source (normally DDR PLL) #CONFIG_EZYNQ_CLK_DDR_DCI_SRC = DDR # DDR DCI clock source (normally DDR PLL)
#CONFIG_EZYNQ_CLK_SMC_SRC = IO # Static memory controller clock source (normally IO PLL) #CONFIG_EZYNQ_CLK_SMC_SRC = IO # Static memory controller clock source (normally IO PLL)
#CONFIG_EZYNQ_CLK_QSPI_SRC = IO # Quad SPI memory controller clock source (normally IO PLL) #CONFIG_EZYNQ_CLK_QSPI_SRC = ARM # Quad SPI memory controller clock source (normally ARM PLL)
#CONFIG_EZYNQ_CLK_GIGE0_SRC = IO # GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO) #CONFIG_EZYNQ_CLK_GIGE0_SRC = IO # GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO)
#CONFIG_EZYNQ_CLK_GIGE1_SRC = IO # GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO) #CONFIG_EZYNQ_CLK_GIGE1_SRC = IO # GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO)
#CONFIG_EZYNQ_CLK_SDIO_SRC = IO # SDIO controller clock source (normally IO PLL) #CONFIG_EZYNQ_CLK_SDIO_SRC = IO # SDIO controller clock source (normally IO PLL)
......
ezynq_ddr.py
View file @ e368919b
...@@ -262,10 +262,10 @@ class EzynqDDR: ...@@ -262,10 +262,10 @@ class EzynqDDR:
ddrc_register_set= self.ddrc_register_set ddrc_register_set= self.ddrc_register_set
ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
self.ddr_init_ddriob(force,warn) # will program to sequence 'MAIN' self.ddr_init_ddriob(force,warn)
regs1=ddriob_register_set.get_register_sets(True,True) regs1=ddriob_register_set.get_register_sets(True,True)
ddrc_register_set.set_initial_state(regs1, True)# add ddrc_register_set.set_initial_state(regs1, True)# add
self.ddr_init_ddrc(force,warn) # will program to sequence 'MAIN' self.ddr_init_ddrc(force,warn)
return ddrc_register_set.get_register_sets(True,True) return ddrc_register_set.get_register_sets(True,True)
def ddr_init_ddrc(self,force=False,warn=False): # will program to sequence 'MAIN' def ddr_init_ddrc(self,force=False,warn=False): # will program to sequence 'MAIN'
...@@ -1439,7 +1439,7 @@ class EzynqDDR: ...@@ -1439,7 +1439,7 @@ class EzynqDDR:
('pref_opt2',0), ('pref_opt2',0),
('update_control',0)),force,warn) ('update_control',0)),force,warn)
#TODO: Remove? #TODO: Remove?
def parse_ddrc_raw_register_set(self,raw_configs,qualifier_char,force=True,warn=True): def parse_ddrc_raw_register_set(self,raw_configs,qualifier_char,force=True,warn=True):
# for i,attribs in enumerate(self.set_attribs): # for i,attribs in enumerate(self.set_attribs):
......
ezynq_slcr_clk_def.py
View file @ e368919b
...@@ -120,11 +120,11 @@ SLCR_CLK_DEFS={ #not all fields are defined currently ...@@ -120,11 +120,11 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
'COMMENTS':'CPU clock control', 'COMMENTS':'CPU clock control',
'FIELDS':{ 'FIELDS':{
'reserved1': {'r':(29,31),'d':0, 'c':'reserved'}, 'reserved1': {'r':(29,31),'d':0, 'c':'reserved'},
'cpu_peri_clkact': {'r':(28,28),'d':0x1, 'c':'Clock active (0 - disabled)'}, # 1 'cpu_peri_clkact': {'r':(28,28),'d':0x1, 'c':'Peripheral clock active (0 - disabled)'},# 1
'cpu_1x_clkact': {'r':(27,27),'d':0x1, 'c':'CPU-1x clock active (0 - disabled)'}, # 1 'cpu_1x_clkact': {'r':(27,27),'d':0x1, 'c':'CPU-1x clock active (0 - disabled)'}, # 1
'cpu_2x_clkact': {'r':(26,26),'d':0x1, 'c':'CPU-2x clock active (0 - disabled)'}, # 1 'cpu_2x_clkact': {'r':(26,26),'d':0x1, 'c':'CPU-2x clock active (0 - disabled)'}, # 1
'cpu_3x2x_clkact': {'r':(25,25),'d':0x1, 'c':'CPU-3x2x clock active (0 - disabled)'},# 1 'cpu_3x2x_clkact': {'r':(25,25),'d':0x1, 'c':'CPU-3x2x clock active (0 - disabled)'}, # 1
'cpu_6x4x_clkact': {'r':(24,24),'d':0x1, 'c':'CPU-6x4x clock active (0 - disabled)'},# 1 'cpu_6x4x_clkact': {'r':(24,24),'d':0x1, 'c':'CPU-6x4x clock active (0 - disabled)'}, # 1
'reserved2': {'r':(14,23),'d':0, 'c':'reserved'}, 'reserved2': {'r':(14,23),'d':0, 'c':'reserved'},
'divisor': {'r':( 8,13),'d':0x4, 'c':'Frequency divisor for the CPU clock source. If PLL is NOT bypassed values 1 and 3 are invalid'}, #0x2 'divisor': {'r':( 8,13),'d':0x4, 'c':'Frequency divisor for the CPU clock source. If PLL is NOT bypassed values 1 and 3 are invalid'}, #0x2
'reserved3': {'r':( 6, 7),'d':0, 'c':'reserved'}, 'reserved3': {'r':( 6, 7),'d':0, 'c':'reserved'},
...@@ -132,16 +132,16 @@ SLCR_CLK_DEFS={ #not all fields are defined currently ...@@ -132,16 +132,16 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
'reserved4': {'r':( 6, 7),'d':0, 'c':'reserved'}}}, 'reserved4': {'r':( 6, 7),'d':0, 'c':'reserved'}}},
'ddr_clk_ctrl': {'OFFS': 0x124,'DFLT':0x18400003,'RW':'RW', # 0xc200003 'ddr_clk_ctrl': {'OFFS': 0x124,'DFLT':0x18400003,'RW':'RW', # 0xc200003
'COMMENTS':'CPU clock control', 'COMMENTS':'DDR_3x (including PHY) and DDR_2X clock control',
'FIELDS':{ 'FIELDS':{
'ddr_2x_clk_divisor': {'r':(26,31),'d':0x6, 'c':'Frequency divisor for ddr_2x clk'}, # 0x3 'ddr_2x_clk_divisor': {'r':(26,31),'d':0x6, 'c':'Frequency divisor for ddr_2x clk'}, # 0x3
'ddr_3x_clk_divisor': {'r':(20,25),'d':0x4, 'c':'Frequency divisor for ddr_3x clk'}, # 0x2 'ddr_3x_clk_divisor': {'r':(20,25),'d':0x4, 'c':'Frequency divisor for ddr_3x clk'}, # 0x2
'reserved1': {'r':( 2,19),'d':0, 'c':'reserved'}, 'reserved1': {'r':( 2,19),'d':0, 'c':'reserved'},
'cpu_2x_clkact': {'r':( 1, 1),'d':0x1, 'c':'1 - ddr_2x clk enabled (0 - disabled)'}, # 0x1 'ddr_2x_clkact': {'r':( 1, 1),'d':0x1, 'c':'1 - ddr_2x clk enabled (0 - disabled)'}, # 0x1
'cpu_3x_clkact': {'r':( 0, 0),'d':0x1, 'c':'1 - ddr_3x clk enabled (0 - disabled)'}}},# 0x1 'ddr_3x_clkact': {'r':( 0, 0),'d':0x1, 'c':'1 - ddr_3x clk enabled (0 - disabled)'}}},# 0x1
'dci_clk_ctrl': {'OFFS': 0x128,'DFLT':0x18400003,'RW':'RW', # 0x302301 'dci_clk_ctrl': {'OFFS': 0x128,'DFLT':0x18400003,'RW':'RW', # 0x302301
'COMMENTS':'CPU clock control', 'COMMENTS':'DDR DCI clock control',
'FIELDS':{ 'FIELDS':{
'reserved1': {'r':(26,31),'d':0, 'c':'reserved'}, 'reserved1': {'r':(26,31),'d':0, 'c':'reserved'},
'divisor1': {'r':(20,25),'d':0x1e, 'c':'Frequency divisor, second stage'}, # 0x3 'divisor1': {'r':(20,25),'d':0x1e, 'c':'Frequency divisor, second stage'}, # 0x3
...@@ -151,7 +151,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently ...@@ -151,7 +151,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
'clkact': {'r':( 0, 0),'d':0x1, 'c':'1 - dci clock enabled (0 - disabled)'}}},# 0x1 'clkact': {'r':( 0, 0),'d':0x1, 'c':'1 - dci clock enabled (0 - disabled)'}}},# 0x1
'aper_clk_ctrl': {'OFFS': 0x12c,'DFLT':0x01ffcccd, 'RW':'RW', # 0x01ec044d (set after peripherals) 'aper_clk_ctrl': {'OFFS': 0x12c,'DFLT':0x01ffcccd, 'RW':'RW', # 0x01ec044d (set after peripherals)
'COMMENTS':'CPU clock control', 'COMMENTS':'AMBA peripherals clock control',
'FIELDS':{ 'FIELDS':{
'reserved1': {'r':(25,31),'d':0, 'c':'reserved'}, 'reserved1': {'r':(25,31),'d':0, 'c':'reserved'},
'smc_cpu_1x_clkact': {'r':(24,24),'d':0x1, 'c':'SMC AMBA clock control (1- enabled, 0- disabled)'}, # 0x1 'smc_cpu_1x_clkact': {'r':(24,24),'d':0x1, 'c':'SMC AMBA clock control (1- enabled, 0- disabled)'}, # 0x1
...@@ -315,10 +315,10 @@ SLCR_CLK_DEFS={ #not all fields are defined currently ...@@ -315,10 +315,10 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
'can1_ref_sel': {'r':(22,22),'d':0, 'c':'CAN1 reference clock selection: 0: from internal PLL, 1 - from MIO based on can1_mux selection'}, 'can1_ref_sel': {'r':(22,22),'d':0, 'c':'CAN1 reference clock selection: 0: from internal PLL, 1 - from MIO based on can1_mux selection'},
'can1_mux': {'r':(16,21),'d':0, 'c':'CAN1 MIO pin selection (valid: 0..53)'}, 'can1_mux': {'r':(16,21),'d':0, 'c':'CAN1 MIO pin selection (valid: 0..53)'},
'reserved2': {'r':( 7,15),'d':0, 'c':'reserved'}, 'reserved2': {'r':( 7,15),'d':0, 'c':'reserved'},
'can1_ref_sel': {'r':( 6, 6),'d':0, 'c':'CAN0 reference clock selection: 0: from internal PLL, 1 - from MIO based on can0_mux selection'}, 'can0_ref_sel': {'r':( 6, 6),'d':0, 'c':'CAN0 reference clock selection: 0: from internal PLL, 1 - from MIO based on can0_mux selection'},
'can1_mux': {'r':( 0, 5),'d':0, 'c':'CAN0 MIO pin selection (valid: 0..53)'}}}, 'can0_mux': {'r':( 0, 5),'d':0, 'c':'CAN0 MIO pin selection (valid: 0..53)'}}},
'spi_clk_ctrl': {'OFFS': 0x164,'DFLT':0xf03,'RW':'RW', # Never set 'dbg_clk_ctrl': {'OFFS': 0x164,'DFLT':0xf03,'RW':'RW', # Never set
'COMMENTS':'SoC debug clock control', 'COMMENTS':'SoC debug clock control',
'FIELDS':{ 'FIELDS':{
'reserved1': {'r':(14,31),'d':0, 'c':'reserved'}, 'reserved1': {'r':(14,31),'d':0, 'c':'reserved'},
......
ezynqcfg.py
View file @ e368919b
...@@ -278,6 +278,8 @@ def write_image(image,name): ...@@ -278,6 +278,8 @@ def write_image(image,name):
bf.close() bf.close()
#========================= #=========================
if not args.verbosity:
args.verbosity=0
raw_configs=read_config(args.configs) raw_configs=read_config(args.configs)
raw_options={n['KEY']:n['VALUE'] for n in raw_configs} raw_options={n['KEY']:n['VALUE'] for n in raw_configs}
permit_undefined_bits=False permit_undefined_bits=False
...@@ -295,7 +297,7 @@ ddr_type=ddr.get_ddr_type() ...@@ -295,7 +297,7 @@ ddr_type=ddr.get_ddr_type()
used_mio_interfaces=mio_regs.get_used_interfaces() used_mio_interfaces=mio_regs.get_used_interfaces()
#clk=ezynq_clk.EzynqClk(regs_masked,ddr_type,permit_undefined_bits=False,force=False,warn=False) #clk=ezynq_clk.EzynqClk(regs_masked,ddr_type,permit_undefined_bits=False,force=False,warn=False)
clk=ezynq_clk.EzynqClk([],ddr_type,used_mio_interfaces,permit_undefined_bits,force,warn_notfit) # will it verify memory type is set? clk=ezynq_clk.EzynqClk(args.verbosity,[],ddr_type,used_mio_interfaces,permit_undefined_bits,force,warn_notfit) # will it verify memory type is set?
clk.parse_parameters(raw_configs) clk.parse_parameters(raw_configs)
clk.calculate_dependent_pars() # will calculate DDR clock, needed for ddr.calculate_dependent_pars() clk.calculate_dependent_pars() # will calculate DDR clock, needed for ddr.calculate_dependent_pars()
...@@ -335,21 +337,74 @@ num_mio_regs=len(reg_sets) ...@@ -335,21 +337,74 @@ num_mio_regs=len(reg_sets)
#adding ddr registers #adding ddr registers
ddr.ddr_init_memory(reg_sets,False,False) ddr.ddr_init_memory(reg_sets,False,False)
#Collecting registers for output reg_sets=ddr.get_new_register_sets() # mio, ddr
num_ddr_regs=len(reg_sets)-num_mio_regs
reg_sets=ddr.get_new_register_sets() #all - mio and ddr
#initialize clocks
# def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False):
clk.clocks_rbl_setup(reg_sets,force) # reg Sets include now MIO and CLK
reg_sets=clk.get_new_register_sets() # mio, ddr and clk
num_clk_regs=len(reg_sets)-num_mio_regs-num_ddr_regs
# #adding ddr registers
# ddr.ddr_init_memory(reg_sets,False,False)
# #Collecting registers for output
#
# reg_sets=ddr.get_new_register_sets() #all - mio,clk and ddr
ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
#ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) #ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f) ezynq_registers.print_html_reg_footer(f)
ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs:num_mio_regs+num_ddr_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f)
ezynq_registers.print_html_reg_header(f, 'CLOCK registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs+num_ddr_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f) ezynq_registers.print_html_reg_footer(f)
# #initialize clocks
# # def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False):
#
# clk.clocks_rbl_setup(reg_sets,force) # reg Sets include now MIO and CLK
# reg_sets=clk.get_new_register_sets() # mio and clk
# num_clk_regs=len(reg_sets)-num_mio_regs
#
#
# #adding ddr registers
# ddr.ddr_init_memory(reg_sets,False,False)
# #Collecting registers for output
#
# reg_sets=ddr.get_new_register_sets() #all - mio,clk and ddr
#
#
# ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
#
# #ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_reg_footer(f)
#
# ezynq_registers.print_html_reg_header(f, 'CLOCK registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs: num_mio_regs+num_clk_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_reg_footer(f)
#
#
# ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs+num_clk_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_reg_footer(f)
#TODO: Need to be modified for the new format #TODO: Need to be modified for the new format
# if 'CONFIG_EZYNQ_UART_LOOPBACK_0' in raw_options: uart_remote_loopback(registers,f, 0,MIO_HTML_MASK) # if 'CONFIG_EZYNQ_UART_LOOPBACK_0' in raw_options: uart_remote_loopback(registers,f, 0,MIO_HTML_MASK)
# if 'CONFIG_EZYNQ_UART_LOOPBACK_1' in raw_options: uart_remote_loopback(registers,f, 1,MIO_HTML_MASK) # if 'CONFIG_EZYNQ_UART_LOOPBACK_1' in raw_options: uart_remote_loopback(registers,f, 1,MIO_HTML_MASK)
......
test.mk
View file @ e368919b
...@@ -274,7 +274,7 @@ CONFIG_EZYNQ_CLK_ARM_SRC = ARM # ARM CPU clock source (normally ARM PLL) ...@@ -274,7 +274,7 @@ CONFIG_EZYNQ_CLK_ARM_SRC = ARM # ARM CPU clock source (normally ARM PLL)
CONFIG_EZYNQ_CLK_DDR_SRC = DDR # DDR (DDR2x, DDR3x) clock source (normally DDR PLL) CONFIG_EZYNQ_CLK_DDR_SRC = DDR # DDR (DDR2x, DDR3x) clock source (normally DDR PLL)
CONFIG_EZYNQ_CLK_DDR_DCI_SRC = DDR # DDR DCI clock source (normally DDR PLL) CONFIG_EZYNQ_CLK_DDR_DCI_SRC = DDR # DDR DCI clock source (normally DDR PLL)
CONFIG_EZYNQ_CLK_SMC_SRC = IO # Static memory controller clock source (normally IO PLL) CONFIG_EZYNQ_CLK_SMC_SRC = IO # Static memory controller clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_QSPI_SRC = IO # Quad SPI memory controller clock source (normally IO PLL) CONFIG_EZYNQ_CLK_QSPI_SRC = ARM # Quad SPI memory controller clock source (normally ARM PLL)
CONFIG_EZYNQ_CLK_GIGE0_SRC = IO # GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO) CONFIG_EZYNQ_CLK_GIGE0_SRC = IO # GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO)
CONFIG_EZYNQ_CLK_GIGE1_SRC = IO # GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO) CONFIG_EZYNQ_CLK_GIGE1_SRC = IO # GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO)
CONFIG_EZYNQ_CLK_SDIO_SRC = IO # SDIO controller clock source (normally IO PLL) CONFIG_EZYNQ_CLK_SDIO_SRC = IO # SDIO controller clock source (normally IO PLL)
......
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