add styling to html (a4821676) · Commits · Elphel / ezynq

LICENSE

0 → 100644

+1499 −0

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ezynq_clk.py

+13 −5

Original line number	Diff line number	Diff line
		@@ -393,24 +393,28 @@ class EzynqClk:
		html_file.write('<h2>System PLL (input clock - %.3f MHz)</h2>'%self.f_in)
		html_file.write('<table border="1">')
		html_file.write(' <tr><th>PLL name</th><th>Frequency</th><th>FDIV</th></tr>\n')
		row_class="even"
		for pll_name in ('ARM','DDR','IO'):
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		name=pll_name+' PLL'
		if pll_name in self.pll_fdivs:
		freq=self.f_in*self.pll_fdivs[pll_name]
		# html_file.write(' <tr><th>'+name+'</th><td>'+('%.3f MHz'%freq)+'</td><td>'+str(self.pll_fdivs[pll_name])+'</td></tr>\n')
		html_file.write(' <tr><th>%s</th><td>%.3f MHz</td><td>%s</td></tr>\n'%(name,freq,str(self.pll_fdivs[pll_name])))
		html_file.write(' <tr class="'+row_class+'"><td><b>%s</b></td><td>%.3f MHz</td><td>%s</td></tr>\n'%(name,freq,str(self.pll_fdivs[pll_name])))
		else:
		html_file.write(' <tr><th>%s</th><td colspan="2" align="center">Unused</td></tr>\n'%name)
		html_file.write(' <tr class="'+row_class+'"><td><b>%s</b></td><td colspan="2" align="center">Unused</td></tr>\n'%name)

		html_file.write('</table>')

		html_file.write('<h2>System Clocks</h2>')
		html_file.write('<table border="1">')
		html_file.write('<table>')
		html_file.write(' <tr><th>Name</th><th>Frequency</th><th>Target</th><th>Error</th><th>PLL</th><th>div 1</th><th>div 2</th><th>Config. name</th><th>Comments</th></tr>\n')

		#TODO - show secondary clocks together with the main ones (frequency only if different from source. Use rowspan
		# self.iface_divs[name]={'SOURCE':source,'VALUE':value, 'FREQ':frequency} #no 'PLL' field
		#CLK_TEMPLATE
		row_class="even"
		for line in CLK_TEMPLATE:
		name=line['NAME']
		if (name in self.iface_divs) and ('PLL' in self.iface_divs[name]):
		@@ -427,13 +431,17 @@ class EzynqClk:
		except:
		div2='-'
		children=list_with_children(name)
		html_file.write(' <tr><th>%s</th><td>%.3f MHz</td><td>%.3f MHz</td><td>%.2f%%</td><td>%s</td><td>%i</td><td>%s</td><td>%s</td><td>%s</td></tr>'%(
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		html_file.write(' <tr class="'+row_class+'"><td><b>%s</b></td><td>%.3f MHz</td><td>%.3f MHz</td><td>%.2f%%</td><td>%s</td><td>%i</td><td>%s</td><td>%s</td><td>%s</td></tr>'%(
		name, freq, target, 100*rel_err, pll, div1, div2, conf_name, description))
		html_file.write(' </tr>')
		for kid_name in children[1:]:
		kid_freq=self.iface_divs[kid_name]['FREQ']
		source=self.iface_divs[kid_name]['SOURCE']
		html_file.write(' <tr><th>%s</th><td>%.3f MHz</td><td colspan="7" align="center">Derived from %s</td></tr>'%(kid_name, kid_freq,source))
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		html_file.write(' <tr class="'+row_class+'"><td><b>%s</b></td><td>%.3f MHz</td><td colspan="7" align="center" style="text-align:center;">Derived from %s</td></tr>'%(kid_name, kid_freq,source))
		# if len(children)>1:
		# print name, "has children=",children
		# elif name in self.iface_divs:

ezynq_feature_config.py

+4 −2

Original line number	Diff line number	Diff line
		@@ -266,6 +266,7 @@ class EzynqFeatures:
		html_file.write('<tr><th>Configuration name</th><th>Value (Target)</th><th>Type/<br/>Choices</th><th>Mandatory</th><th>Origin</th><th>Default</th><th>Description</th></tr>\n')
		# print self.get_par_names()
		# for name in self.pars:
		row_class="even"
		for name in self.get_par_names():
		# name= self.config_names[conf_name]
		feature= self.defs[name]
		@@ -307,8 +308,9 @@ class EzynqFeatures:

		# if name=='BAUD_RATE':
		# print value

		html_file.write('<tr><th>'+feature['CONF_NAME']+'</th><td>'+str(value)+'</td><td>'+par_type+
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		html_file.write('<tr class="'+row_class+'"><td><b>'+feature['CONF_NAME']+'</b></td><td>'+str(value)+'</td><td>'+par_type+
		'</td><td>'+('-','Y')[feature['MANDATORY']]+'</td><td>'+origin+'</td><td>'+str(feature['DEFAULT'])+'</td><td>'+feature['DESCRIPTION']+'</td></tr>\n')
		html_file.write('</table>\n')

ezynq_mio.py

+4 −1

Original line number	Diff line number	Diff line
		@@ -688,8 +688,11 @@ class EzynqMIO:
		for c in self.mio_interfaces:
		f.write('<th>'+c['NAME']+'<br/>'+c['PRINT_CHANNEL']+' </th>')
		f.write(' </tr>\n')
		row_class="even"
		for pinnum,mio_pin in enumerate(self.mio):
		f.write('<th>'+str(pinnum)+'</th>')
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		f.write('<tr class="'+row_class+'"><td><b>'+str(pinnum)+'</b></td>')
		if MIO_HTML_MASK & 1:
		f.write('<td>'+hex(mio_pin['ADDR'])+'</td>')
		if MIO_HTML_MASK & 2:

ezynq_registers.py

+24 −13

Original line number	Diff line number	Diff line
		@@ -32,7 +32,7 @@ def print_html_reg_header(html_file, title='',show_bit_fields=True, show_comment
		if show_bit_fields:
		html_file.write('<tr><th>Address/<br/>bit field</th><th>Register name/<br>Bit field name</th><th>R/W</th><th>Value</th><th>Previous<br/>Value</th><th>Default</th>\n')
		else:
		html_file.write('<tr><th>Address</th><th>Register name</th><th>R/W</th><th>Value</th><th>Default</th>\n')
		html_file.write('<tr><th>Address</th><th>Register name</th><th>R/W</th><th>Value</th><th>Previous<br/>Value</th><th>Default</th>\n')
		if show_comments:
		html_file.write('<th>Comments</th>')
		html_file.write('</tr>')
		@@ -52,6 +52,7 @@ def print_html_registers(html_file, reg_sets, from_index, show_bit_fields=True,

		# new_sets.append((addr,data,mask,self.module_name,register_name,self.registers[register_name]))
		current_reg_state={} #address: (data,mask)
		row_class="even"
		for index, (op,addr, data, mask, module_name, register_name, r_def) in enumerate (reg_sets):
		# if (op != 's'):
		# continue # TODO: add handling of test conditions later
		@@ -87,28 +88,29 @@ def print_html_registers(html_file, reg_sets, from_index, show_bit_fields=True,
		if index<from_index: # just accumulate previous history of the register mask/values, no output
		continue

		html_file.write('<tr>\n')
		try:
		comments=r_def['COMMENTS']
		except:
		comments=''

		if show_bit_fields:
		html_file.write('<tr class="special"><b>\n')
		if op == 's':
		html_file.write(' <th>0x%8x</th><th>%s.%s</th><th>%s</th><th>%s</th><th>%s</th><th>%s</th>'%
		html_file.write(' <td>0x%8x</td><td>%s.%s</td><td>%s</td><td>%s</td><td>%s</td><td>%s</td>'%
		(addr, module_name,register_name,rw, opt_hex(new_data), prev_sdata, opt_hex(dflt_data)))
		elif op == '=':
		html_file.write(' <th>0x%8x</th><th>%s.%s</th><th colspan="4">Wait for (reg & %s) == %s</th>'%
		html_file.write(' <td>0x%8x</td><td>%s.%s</td><td colspan="4">Wait for (reg & %s) == %s</td>'%
		(addr, module_name,register_name, opt_hex(mask), opt_hex(data)))
		elif op == '!':
		html_file.write(' <th>0x%8x</th><th>%s.%s</th><th colspan="4">Wait for (reg & %s) != %s</th>'%
		html_file.write(' <td>0x%8x</td><td>%s.%s</td><td colspan="4">Wait for (reg & %s) != %s</td>'%
		(addr, module_name,register_name, opt_hex(mask), opt_hex(data)))
		else:
		raise Exception ('Invalid register operation: %s for register 0x%08x'%(op,addr))
		if show_comments:
		html_file.write('<th>%s</th>'%comments)
		html_file.write('\n</tr>\n')
		html_file.write('<td>%s</td>'%comments)
		html_file.write('\n</b></tr>\n')
		if 'FIELDS' in r_def:
		row_class="even"
		#sort bit fields
		for f_name in [pair[0] for pair in sorted([(nam,r_def['FIELDS'][nam]['r'][0]) for nam in r_def['FIELDS']], key = lambda rr: -rr[1])]:
		field=r_def['FIELDS'][f_name]
		@@ -127,13 +129,19 @@ def print_html_registers(html_file, reg_sets, from_index, show_bit_fields=True,
		f_prev=(old_data & f_mask) >> r[0]
		field_prev=('-', opt_hex(f_prev))[prev_sdata!='-']
		modified=f_data != f_prev
		html_file.write(' <tr><td>%i:%i</td><td>%s</td><td>%s</td><td>%s%s%s</td><td>%s</td><td>%s</td>'%
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		html_file.write(' <tr class="'+row_class+'"><td>%i:%i</td><td>%s</td><td>%s</td><td>%s%s%s</td><td>%s</td><td>%s</td>'%
		(r[0],r[1], f_name, f_rw,('','<b>')[modified],opt_hex(f_data),('','</b>')[modified],field_prev,opt_hex(f_dflt)))
		elif op == '=':
		html_file.write(' <tr><td>%i:%i</td><td>%s</td><td colspan="4">Wait for bit(s) == %s</th>'%
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		html_file.write(' <tr class="'+row_class+'"><td>%i:%i</td><td>%s</td><td colspan="4">Wait for bit(s) == %s</td>'%
		(r[0],r[1], f_name, opt_hex(f_data)))
		elif op == '!':
		html_file.write(' <tr><td>%i:%i</td><td>%s</td><td colspan="4">Wait for bit(s) != %s</th>'%
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		html_file.write(' <tr class="'+row_class+'"><td>%i:%i</td><td>%s</td><td colspan="4">Wait for bit(s) != %s</td>'%
		(r[0],r[1], f_name, opt_hex(f_data)))

		else:
		@@ -147,14 +155,17 @@ def print_html_registers(html_file, reg_sets, from_index, show_bit_fields=True,
		html_file.write('<td>%s</td>'%f_comments)
		html_file.write('\n</tr>\n')
		else:
		if row_class=="odd": row_class="even"
		else: row_class="odd"
		html_file.write('<tr class="'+row_class+'">\n')
		if op == 's':
		html_file.write(' <th>0x%8x</th><td>%s.%s</td><td>%s</td><td><b>%s</b></td><td>%s</td><td>%s</td>'%
		html_file.write(' <td><b>0x%8x</b></td><td>%s.%s</td><td>%s</td><td><b>%s</b></td><td>%s</td><td>%s</td>'%
		(addr, module_name,register_name,rw,opt_hex(new_data), prev_sdata, opt_hex(dflt_data)))
		elif op == '=':
		html_file.write(' <th>0x%8x</th><td>%s.%s</td><tdcolspan="4"><b>Wait for (reg & %s) == %s</b></td>'%
		html_file.write(' <td><b>0x%8x</b></td><td>%s.%s</td><tdcolspan="4"><b>Wait for (reg & %s) == %s</b></td>'%
		(addr, module_name,register_name,opt_hex(mask),opt_hex(data)))
		elif op == '!':
		html_file.write(' <th>0x%8x</th><td>%s.%s</td><tdcolspan="4"><b>Wait for (reg & %s) != %s</b></td>'%
		html_file.write(' <td><b>0x%8x</b></td><td>%s.%s</td><tdcolspan="4"><b>Wait for (reg & %s) != %s</b></td>'%
		(addr, module_name,register_name,opt_hex(mask),opt_hex(data)))
		else:
		raise Exception ('Invalid register operation: %s for register 0x%08x'%(op,addr))

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