Loading ezynq_clk.py +0 −4 Original line number Diff line number Diff line Loading @@ -660,10 +660,6 @@ class EzynqClk: usb0_cpu_1x_clkact = 1 if (iface['NAME']=='USB') and (iface['CHANNEL']==1) : usb1_cpu_1x_clkact = 1 # for ii in self.iface_divs: # print ii # for ii in self.used_mio_interfaces: # print ii dma_cpu_2x_clkact = 1 # 0x1 clk_register_set.set_bitfields('aper_clk_ctrl',( # AMBA peripherals clock control # ('reserved1', 0), # Loading Loading
ezynq_clk.py +0 −4 Original line number Diff line number Diff line Loading @@ -660,10 +660,6 @@ class EzynqClk: usb0_cpu_1x_clkact = 1 if (iface['NAME']=='USB') and (iface['CHANNEL']==1) : usb1_cpu_1x_clkact = 1 # for ii in self.iface_divs: # print ii # for ii in self.used_mio_interfaces: # print ii dma_cpu_2x_clkact = 1 # 0x1 clk_register_set.set_bitfields('aper_clk_ctrl',( # AMBA peripherals clock control # ('reserved1', 0), # Loading