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ezynq
Commit 98f98457 authored by Andrey Filippov's avatar Andrey Filippov
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removed commented out code

parent 2f4f6bc6
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ezynq_clk.py
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...@@ -660,10 +660,6 @@ class EzynqClk: ...@@ -660,10 +660,6 @@ class EzynqClk:
usb0_cpu_1x_clkact = 1 usb0_cpu_1x_clkact = 1
if (iface['NAME']=='USB') and (iface['CHANNEL']==1) : if (iface['NAME']=='USB') and (iface['CHANNEL']==1) :
usb1_cpu_1x_clkact = 1 usb1_cpu_1x_clkact = 1
# for ii in self.iface_divs:
# print ii
# for ii in self.used_mio_interfaces:
# print ii
dma_cpu_2x_clkact = 1 # 0x1 dma_cpu_2x_clkact = 1 # 0x1
clk_register_set.set_bitfields('aper_clk_ctrl',( # AMBA peripherals clock control clk_register_set.set_bitfields('aper_clk_ctrl',( # AMBA peripherals clock control
# ('reserved1', 0), # # ('reserved1', 0), #
......
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