Commit 97cc5c68 authored by Andrey Filippov's avatar Andrey Filippov

Continue with clocks

parent dde94af2
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This diff is collapsed.
...@@ -166,6 +166,15 @@ MIO_TEMPLATES = { ...@@ -166,6 +166,15 @@ MIO_TEMPLATES = {
((10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50), (9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53))}, ((10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50), (9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53))},
{'NAME':'TX', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':1, 'PINS': {'NAME':'TX', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':1, 'PINS':
((11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51), (8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52))}), ((11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51), (8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52))}),
'CAN_ECLK':( # Docs say that any MIO pin can be used, but 7,8 are out only, so probably they can not be assigned
{'NAME':'ECLK', 'TRISTATE':True, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':0, 'PINS':(
(0,1,2,3,4,5,6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,
31,32,33,34,35,36,37.38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53),
(0,1,2,3,4,5,6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,
31,32,33,34,35,36,37.38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53))},),
'UART':( 'UART':(
{'NAME':'RX', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':7, 'PINS': {'NAME':'RX', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':7, 'PINS':
((10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50), (9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53))}, ((10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50), (9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53))},
...@@ -211,7 +220,7 @@ MIO_TEMPLATES = { ...@@ -211,7 +220,7 @@ MIO_TEMPLATES = {
MIO_INTERFACES=[ MIO_INTERFACES=[
{'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_0', 'IFACE':'QUADSPI', 'CHANNEL':0}, {'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_0', 'IFACE':'QUADSPI', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_1', 'IFACE':'QUADSPI_FBCLK','CHANNEL':1}, {'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_1', 'IFACE':'QUADSPI_FBCLK','CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_FBCLK', 'IFACE':'ETH', 'CHANNEL':0}, {'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_FBCLK', 'IFACE':'QUADSPI_FBCLK','CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_0', 'IFACE':'ETH', 'CHANNEL':0}, {'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_0', 'IFACE':'ETH', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_1', 'IFACE':'ETH', 'CHANNEL':1}, {'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_1', 'IFACE':'ETH', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_MDIO', 'IFACE':'MDIO', 'CHANNEL':0}, {'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_MDIO', 'IFACE':'MDIO', 'CHANNEL':0},
...@@ -728,6 +737,14 @@ class EzynqMIO: ...@@ -728,6 +737,14 @@ class EzynqMIO:
print i, mio_pin print i, mio_pin
print mio_dflts print mio_dflts
def get_used_interfaces(self):
# return self.mio_interfaces # all data
# for iface in self.mio_interfaces:
# print iface
# return {iface['NAME']:iface['CHANNEL'] for iface in self.mio_interfaces}
return [{'NAME':iface['NAME'],'CHANNEL':iface['CHANNEL'],'PIN':iface['IFACE'].items()[0][1]['PIN']} for iface in self.mio_interfaces]
###### not used as they are prohibited by RBL ###### not used as they are prohibited by RBL
# def output_gpio_out(registers,f,MIO_HTML_MASK): # def output_gpio_out(registers,f,MIO_HTML_MASK):
# if f: # if f:
......
...@@ -292,8 +292,10 @@ ddr=ezynq_ddr.EzynqDDR([],permit_undefined_bits, force, warn_notfit) #regs_maske ...@@ -292,8 +292,10 @@ ddr=ezynq_ddr.EzynqDDR([],permit_undefined_bits, force, warn_notfit) #regs_maske
ddr.parse_parameters(raw_configs) ddr.parse_parameters(raw_configs)
ddr_type=ddr.get_ddr_type() ddr_type=ddr.get_ddr_type()
used_mio_interfaces=mio_regs.get_used_interfaces()
#clk=ezynq_clk.EzynqClk(regs_masked,ddr_type,permit_undefined_bits=False,force=False,warn=False) #clk=ezynq_clk.EzynqClk(regs_masked,ddr_type,permit_undefined_bits=False,force=False,warn=False)
clk=ezynq_clk.EzynqClk([],ddr_type,permit_undefined_bits,force,warn_notfit) # will it verify memory type is set? clk=ezynq_clk.EzynqClk([],ddr_type,used_mio_interfaces,permit_undefined_bits,force,warn_notfit) # will it verify memory type is set?
clk.parse_parameters(raw_configs) clk.parse_parameters(raw_configs)
clk.calculate_dependent_pars() # will calculate DDR clock, needed for ddr.calculate_dependent_pars() clk.calculate_dependent_pars() # will calculate DDR clock, needed for ddr.calculate_dependent_pars()
......
...@@ -240,11 +240,20 @@ CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY = 160 ...@@ -240,11 +240,20 @@ CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY = 160 CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY = 160 CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY = 160
############# Main clock settings ############# ############# Main clock settings #############
CONFIG_EZYNQ_CLK_PS_MHZ = 33.333333 # PS_CLK System clock input frequency (MHz) CONFIG_EZYNQ_CLK_PS_MHZ = 33.333333 # PS_CLK System clock input frequency (MHz)
CONFIG_EZYNQ_CLK_DDR_MHZ = 533.333333 # DDR clock frequency - DDR_3X (MHz) CONFIG_EZYNQ_CLK_DDR_MHZ = 533.333333 # DDR clock frequency - DDR_3X (MHz)
CONFIG_EZYNQ_CLK_ARM_MHZ = 640#667 # ARM CPU clock frequency cpu_6x4x (MHz) CONFIG_EZYNQ_CLK_ARM_MHZ = 667 # ARM CPU clock frequency cpu_6x4x (MHz)
CONFIG_EZYNQ_CLK_CPU_MODE = 6_2_1 # CPU clocks set 6:2:1 (6:3:2:1) or 4:2:1 (4:2:2:1) CONFIG_EZYNQ_CLK_CPU_MODE = 6_2_1 # CPU clocks set 6:2:1 (6:3:2:1) or 4:2:1 (4:2:2:1)
CONFIG_EZYNQ_CLK_FPGA0 = 50.0 # FPGA 0 clock frequency (MHz)
CONFIG_EZYNQ_CLK_FPGA1 = 50.0 # FPGA 1 clock frequency (MHz)
CONFIG_EZYNQ_CLK_FPGA2 = 50.0 # FPGA 2 clock frequency (MHz)
CONFIG_EZYNQ_CLK_FPGA3 = 50.0 # FPGA 3 clock frequency (MHz)
CONFIG_EZYNQ_CLK_FPGA0_SRC = IO # FPGA 0 clock source
CONFIG_EZYNQ_CLK_FPGA1_SRC = IO # FPGA 1 clock source
CONFIG_EZYNQ_CLK_FPGA2_SRC = IO # FPGA 2 clock source
CONFIG_EZYNQ_CLK_FPGA3_SRC = IO # FPGA 3 clock source
############# Normally do not need to be modified ############# ############# Normally do not need to be modified #############
CONFIG_EZYNQ_CLK_DDR_DCI_MHZ = 10.0 # DDR DCI clock frequency (MHz). Normally 10 Mhz'}, CONFIG_EZYNQ_CLK_DDR_DCI_MHZ = 10.0 # DDR DCI clock frequency (MHz). Normally 10 Mhz'},
...@@ -252,27 +261,32 @@ CONFIG_EZYNQ_CLK_DDR2X_MHZ = 355.556 # DDR2X clock frequency (MHz). Does not nee ...@@ -252,27 +261,32 @@ CONFIG_EZYNQ_CLK_DDR2X_MHZ = 355.556 # DDR2X clock frequency (MHz). Does not nee
CONFIG_EZYNQ_CLK_DDR_DCI_MHZ= 10.0 # DDR DCI clock frequency (MHz). Normally 10Mhz CONFIG_EZYNQ_CLK_DDR_DCI_MHZ= 10.0 # DDR DCI clock frequency (MHz). Normally 10Mhz
CONFIG_EZYNQ_CLK_SMC_MHZ = 100.0 # Static memory controller clock frequency (MHz). Normally 100 Mhz CONFIG_EZYNQ_CLK_SMC_MHZ = 100.0 # Static memory controller clock frequency (MHz). Normally 100 Mhz
CONFIG_EZYNQ_CLK_QSPI_MHZ = 200.0 # Quad SPI memory controller clock frequency (MHz). Normally 200 Mhz CONFIG_EZYNQ_CLK_QSPI_MHZ = 200.0 # Quad SPI memory controller clock frequency (MHz). Normally 200 Mhz
CONFIG_EZYNQ_CLK_GIGE_MHZ = 125.0 # GigE Ethernet controller reference clock frequency (MHz). Normally 125 Mhz CONFIG_EZYNQ_CLK_GIGE0_MHZ = 125.0 # GigE 0 Ethernet controller reference clock frequency (MHz). Normally 125 Mhz
CONFIG_EZYNQ_CLK_GIGE1_MHZ = 125.0 # GigE 1 Ethernet controller reference clock frequency (MHz). Normally 125 Mhz
CONFIG_EZYNQ_CLK_SDIO_MHZ = 100.0 # SDIO controller reference clock frequency (MHz). Normally 100 Mhz CONFIG_EZYNQ_CLK_SDIO_MHZ = 100.0 # SDIO controller reference clock frequency (MHz). Normally 100 Mhz
CONFIG_EZYNQ_CLK_UART_MHZ = 25.0 # UART controller reference clock frequency (MHz). Normally 25 Mhz CONFIG_EZYNQ_CLK_UART_MHZ = 25.0 # UART controller reference clock frequency (MHz). Normally 25 Mhz
CONFIG_EZYNQ_CLK_SPI_MHZ = 200.0 # SPI controller reference clock frequency (MHz). Normally 200 Mhz CONFIG_EZYNQ_CLK_SPI_MHZ = 200.0 # SPI controller reference clock frequency (MHz). Normally 200 Mhz
CONFIG_EZYNQ_CLK_CAN_MHZ = 100.0 # CAN controller reference clock frequency (MHz). Normally 100 Mhz CONFIG_EZYNQ_CLK_CAN_MHZ = 100.0 # CAN controller reference clock frequency (MHz). Normally 100 Mhz
CONFIG_EZYNQ_CLK_PCAP_MHZ = 200.0 # PCAP clock frequency (MHz). Normally 200 Mhz CONFIG_EZYNQ_CLK_PCAP_MHZ = 200.0 # PCAP clock frequency (MHz). Normally 200 Mhz
CONFIG_EZYNQ_CLK_TRACE_MHZ = 100.0 # Trace Port clock frequency (MHz). Normally 100 Mhz CONFIG_EZYNQ_CLK_TRACE_MHZ = 100.0 # Trace Port clock frequency (MHz). Normally 100 Mhz
CONFIG_EZYNQ_CLK_PLL_FCLK_MHZ = 50.0 # PLL DCLK clock frequency (MHz). Normally 50 Mhz CONFIG_EZYNQ_CLK_ARM_SRC = ARM # ARM CPU clock source (normally ARM PLL)
CONFIG_EZYNQ_CLK_ARM_SRC = ARM # ARM CPU clock source (normally ARM PLL)'}, CONFIG_EZYNQ_CLK_DDR_SRC = DDR # DDR (DDR2x, DDR3x) clock source (normally DDR PLL)
CONFIG_EZYNQ_CLK_DDR_SRC = DDR # DDR (DDR2x, DDR3x) clock source (normally DDR PLL)'}, CONFIG_EZYNQ_CLK_DCI_SRC = DDR # DDR DCI clock source (normally DDR PLL)
CONFIG_EZYNQ_CLK_DCI_SRC = DDR # DDR DCI clock source (normally DDR PLL)'}, CONFIG_EZYNQ_CLK_SMC_SRC = IO # Static memory controller clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_SMC_SRC = IO # Static memory controller clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_QSPI_SRC = IO # Quad SPI memory controller clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_QSPI_SRC = IO # Quad SPI memory controller clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_GIGE0_SRC = IO # GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO)
CONFIG_EZYNQ_CLK_GIGE_SRC = IO # GigE Ethernet controller clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_GIGE1_SRC = IO # GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO)
CONFIG_EZYNQ_CLK_SDIO_SRC = IO # SDIO controller clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_SDIO_SRC = IO # SDIO controller clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_UART_SRC = IO # UART controller clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_UART_SRC = IO # UART controller clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_SPI_SRC = IO # SPI controller clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_SPI_SRC = IO # SPI controller clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_CAN_SRC = IO # CAN controller clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_CAN_SRC = IO # CAN controller clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_PCAP_SRC = IO # PCAP controller clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_PCAP_SRC = IO # PCAP controller clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_TRACE_SRC = IO # Trace Port clock source (normally IO PLL)'}, CONFIG_EZYNQ_CLK_TRACE_SRC = IO # Trace Port clock source (normally IO PLL)
CONFIG_EZYNQ_CLK_PLL_FCLK_SRC = IO # PLL FCLK clock source (normally IO PLL)'},
CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE = DDR3 # DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE = DDR3 # DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V)
##### performance data, final values (overwrite calculated) ##### ##### performance data, final values (overwrite calculated) #####
......
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