Addin generation of reset of all used peripherals, removing same one form UART initialization (52149147) · Commits · Elphel / ezynq

ezynq_clk.py

+82 −0

Original line number	Diff line number	Diff line
		@@ -563,6 +563,88 @@ class EzynqClk:
		clk_register_set.set_bitfields('arm_pll_ctrl',(('pll_bypass_force', 0),
		('pll_bypass_qual', 0)),force,warn)
		return self.get_new_register_sets()
		# reset instantiated peripherals

		def reset_peripherals(self,current_reg_sets,force=False,warn=False):
		# print ezynq_slcr_clk_def.RESETS
		extra_interfaces=[{'NAME':'DMA'}]
		used_interfaces=self.used_mio_interfaces+extra_interfaces
		def set_resets(reset_on):
		for iface in used_interfaces:
		name=iface['NAME']
		if name in ezynq_slcr_clk_def.RESETS:
		rst=ezynq_slcr_clk_def.RESETS[name]
		if len(rst)>1:
		rst=rst[iface['CHANNEL']]
		else:
		rst=rst[0]
		fields=[]
		for fld in rst['FIELDS']:
		# print name, fld
		fields.append((fld['FIELD_NAME'],fld[('OFF','RST')[reset_on]]))
		rst_register_set.set_bitfields(rst['REG'],tuple(fields),force,warn)
		rst_register_set=self.clk_register_set
		rst_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
		set_resets(True)
		rst_register_set.flush()
		set_resets(False)
		return rst_register_set.get_register_sets(True,True)
		#
		# self.used_mio_interfaces
		# uart_register_set=self.uart_register_set
		# slcr_register_set=self.slcr_register_set
		# slcr_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
		# slcr_register_set.set_bitfields('uart_rst_ctrl',( # dflt=0
		# ('uart1_ref_rst', self.channel==1), # UART 1 reference clock domain reset: 0 - normal, 1 - reset
		# ('uart0_ref_rst', self.channel==0), # UART 0 reference clock domain reset: 0 - normal, 1 - reset
		# ('uart1_cpu1x_rst', self.channel==1), # UART 1 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		# ('uart0_cpu1x_rst', self.channel==0)),force,warn) #UART 0 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		# slcr_register_set.flush()
		# slcr_register_set.set_bitfields('uart_rst_ctrl',( # dflt=0
		# ('uart1_ref_rst', 0), # UART 1 reference clock domain reset: 0 - normal, 1 - reset
		# ('uart0_ref_rst', 0), # UART 0 reference clock domain reset: 0 - normal, 1 - reset
		# ('uart1_cpu1x_rst', 0), # UART 1 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		# ('uart0_cpu1x_rst', 0)),force,warn) #UART 0 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		# reg_sets=slcr_register_set.get_register_sets(sort_addr=True,apply_new=True)

		# RESETS= {'DMA': ({'REG':'dmac_rst_ctrl','FIELDS':({'FIELD_NAME':'dmac_rst', 'RST':1,'OFF':0})}),
		# 'USB': ({'REG':'usb_rst_ctrl', 'FIELDS':({'FIELD_NAME':'usb0_cpu1x_rst', 'RST':1,'OFF':0})},
		# {'REG':'usb_rst_ctrl', 'FIELDS':({'FIELD_NAME':'usb1_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'ETH': ({'REG':'gem_rst_ctrl', 'FIELDS':({'FIELD_NAME':'gem0_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'gem0_rx_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'gem0_cpu1x_rst', 'RST':1,'OFF':0})},
		# {'REG':'gem_rst_ctrl', 'FIELDS':({'FIELD_NAME':'gem1_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'gem1_rx_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'gem1_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'SDIO':({'REG':'sdio_rst_ctrl','FIELDS':({'FIELD_NAME':'sdio0_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'sdio0_cpu1x_rst', 'RST':1,'OFF':0})},
		# {'REG':'sdio_rst_ctrl','FIELDS':({'FIELD_NAME':'sdio1_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'sdio1_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'SPI': ({'REG':'spi_rst_ctrl', 'FIELDS':({'FIELD_NAME':'spi0_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'spi0_cpu1x_rst', 'RST':1,'OFF':0})},
		# {'REG':'spi_rst_ctrl', 'FIELDS':({'FIELD_NAME':'spi1_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'spi1_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'CAN': ({'REG':'can_rst_ctrl', 'FIELDS':({'FIELD_NAME':'can0_cpu1x_rst', 'RST':1,'OFF':0})},
		# {'REG':'can_rst_ctrl', 'FIELDS':({'FIELD_NAME':'can1_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'I2C': ({'REG':'i2c_rst_ctrl', 'FIELDS':({'FIELD_NAME':'i2c0_cpu1x_rst', 'RST':1,'OFF':0})},
		# {'REG':'i2c_rst_ctrl', 'FIELDS':({'FIELD_NAME':'i2c1_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'UART':({'REG':'uart_rst_ctrl','FIELDS':({'FIELD_NAME':'uart0_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'uart0_cpu1x_rst', 'RST':1,'OFF':0})},
		# {'REG':'uart_rst_ctrl','FIELDS':({'FIELD_NAME':'uart1_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'uart1_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'GPIO':({'REG':'gpio_rst_ctrl','FIELDS':({'FIELD_NAME':'gpio_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'QSPI':({'REG':'qspi_rst_ctrl','FIELDS':({'FIELD_NAME':'qspi_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'qspi_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'NAND':({'REG':'smc_rst_ctrl', 'FIELDS':({'FIELD_NAME':'smc_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'smc_cpu1x_rst', 'RST':1,'OFF':0})}),
		# 'NOR': ({'REG':'smc_rst_ctrl', 'FIELDS':({'FIELD_NAME':'smc_ref_rst', 'RST':1,'OFF':0},
		# {'FIELD_NAME':'smc_cpu1x_rst', 'RST':1,'OFF':0})}),
		# }







		#clocks setup

ezynq_slcr_clk_def.py

+42 −7

Original line number	Diff line number	Diff line
		@@ -503,13 +503,13 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
		'COMMENTS':'Central interconnect software reset control',
		'FIELDS':{
		'reserved': {'r':( 1,31),'d':0, 'c':'reserved'},
		'ddr_rst': {'r':( 0, 0),'d':0, 'c':'Central interconnect reset: 0 - normal, 1 - reset. Make sure AXI does not have outstanding transactions and the bus is idle'}}},
		'topsw_rst': {'r':( 0, 0),'d':0, 'c':'Central interconnect reset: 0 - normal, 1 - reset. Make sure AXI does not have outstanding transactions and the bus is idle'}}},

		'dmac_rst_ctrl': {'OFFS': 0x20c,'DFLT':0,'RW':'RW', # Never set
		'COMMENTS':'DMA controller software reset control',
		'FIELDS':{
		'reserved': {'r':( 1,31),'d':0, 'c':'reserved'},
		'ddr_rst': {'r':( 0, 0),'d':0, 'c':'DMA controller reset: 0 - normal, 1 - reset (and write enable DMAC trust zone register)'}}},
		'dmac_rst': {'r':( 0, 0),'d':0, 'c':'DMA controller reset: 0 - normal, 1 - reset (and write enable DMAC trust zone register)'}}},

		'usb_rst_ctrl': {'OFFS': 0x210,'DFLT':0,'RW':'RW', # Never set
		'COMMENTS':'USB software reset control',
		@@ -549,7 +549,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
		'spi1_cpu1x_rst': {'r':( 1, 1),'d':0, 'c':'SPI 1 CPU_1x clock domain reset: 0 - normal, 1 - reset'},
		'spi0_cpu1x_rst': {'r':( 0, 0),'d':0, 'c':'SPI 0 CPU_1x clock domain reset: 0 - normal, 1 - reset'}}},

		'cam_rst_ctrl': {'OFFS': 0x220,'DFLT':0,'RW':'RW', # Never set
		'can_rst_ctrl': {'OFFS': 0x220,'DFLT':0,'RW':'RW', # Never set
		'COMMENTS':'CAN software reset control',
		'FIELDS':{
		'reserved1': {'r':( 4,31),'d':0, 'c':'reserved'},
		@@ -580,15 +580,15 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
		'reserved': {'r':( 1,31),'d':0, 'c':'reserved'},
		'gpio_cpu1x_rst': {'r':( 0, 0),'d':0, 'c':'GPIO 0 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset'}}},

		'lqspi_rst_ctrl': {'OFFS': 0x230,'DFLT':0,'RW':'RW', # Never set
		'qspi_rst_ctrl': {'OFFS': 0x230,'DFLT':0,'RW':'RW', # Never set
		'COMMENTS':'Quad SPI software reset control for reference clock and CPU_1x (AMBA) clock domains',
		'FIELDS':{
		'reserved': {'r':( 2,31),'d':0, 'c':'reserved'},
		'qspi_ref_rst': {'r':( 1, 1),'d':0, 'c':'QSPI reference clock domain reset: 0 - normal, 1 - reset'},
		'lqspi_cpu1x_rst': {'r':( 0, 0),'d':0, 'c':'QSPI CPU_1x clock domain reset: 0 - normal, 1 - reset'}}},
		'qspi_cpu1x_rst': {'r':( 0, 0),'d':0, 'c':'QSPI CPU_1x clock domain reset: 0 - normal, 1 - reset'}}},

		'smc_rst_ctrl': {'OFFS': 0x234,'DFLT':0,'RW':'RW', # Never set
		'COMMENTS':'Quad SPI software reset control for reference clock and CPU_1x (AMBA) clock domains',
		'COMMENTS':'SMS software reset control for reference clock and CPU_1x (AMBA) clock domains',
		'FIELDS':{
		'reserved': {'r':( 2,31),'d':0, 'c':'reserved'},
		'smc_ref_rst': {'r':( 1, 1),'d':0, 'c':'SMC reference clock domain reset: 0 - normal, 1 - reset'},
		@@ -780,3 +780,38 @@ PLL_PARS=(( 13, 2,6,750),
		((37,40),2,12,250),
		((41,47),3,12,250),
		((48,66),3,12,250))

		RESETS= {'DMA': ({'REG':'dmac_rst_ctrl','FIELDS':({'FIELD_NAME':'dmac_rst', 'RST':1,'OFF':0},)},),
		'USB': ({'REG':'usb_rst_ctrl', 'FIELDS':({'FIELD_NAME':'usb0_cpu1x_rst', 'RST':1,'OFF':0},)},
		{'REG':'usb_rst_ctrl', 'FIELDS':({'FIELD_NAME':'usb1_cpu1x_rst', 'RST':1,'OFF':0},)} ),
		'ETH': ({'REG':'gem_rst_ctrl', 'FIELDS':({'FIELD_NAME':'gem0_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'gem0_rx_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'gem0_cpu1x_rst', 'RST':1,'OFF':0} )},
		{'REG':'gem_rst_ctrl', 'FIELDS':({'FIELD_NAME':'gem1_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'gem1_rx_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'gem1_cpu1x_rst', 'RST':1,'OFF':0})}),
		'SDIO':({'REG':'sdio_rst_ctrl','FIELDS':({'FIELD_NAME':'sdio0_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'sdio0_cpu1x_rst', 'RST':1,'OFF':0} )},
		{'REG':'sdio_rst_ctrl','FIELDS':({'FIELD_NAME':'sdio1_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'sdio1_cpu1x_rst', 'RST':1,'OFF':0} )} ),
		'SPI': ({'REG':'spi_rst_ctrl', 'FIELDS':({'FIELD_NAME':'spi0_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'spi0_cpu1x_rst', 'RST':1,'OFF':0} )},
		{'REG':'spi_rst_ctrl', 'FIELDS':({'FIELD_NAME':'spi1_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'spi1_cpu1x_rst', 'RST':1,'OFF':0} )} ),
		'CAN': ({'REG':'can_rst_ctrl', 'FIELDS':({'FIELD_NAME':'can0_cpu1x_rst', 'RST':1,'OFF':0},)},
		{'REG':'can_rst_ctrl', 'FIELDS':({'FIELD_NAME':'can1_cpu1x_rst', 'RST':1,'OFF':0},)} ),
		'I2C': ({'REG':'i2c_rst_ctrl', 'FIELDS':({'FIELD_NAME':'i2c0_cpu1x_rst', 'RST':1,'OFF':0},)},
		{'REG':'i2c_rst_ctrl', 'FIELDS':({'FIELD_NAME':'i2c1_cpu1x_rst', 'RST':1,'OFF':0},)} ),
		'UART':({'REG':'uart_rst_ctrl','FIELDS':({'FIELD_NAME':'uart0_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'uart0_cpu1x_rst', 'RST':1,'OFF':0} )},
		{'REG':'uart_rst_ctrl','FIELDS':({'FIELD_NAME':'uart1_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'uart1_cpu1x_rst', 'RST':1,'OFF':0} )} ),
		'GPIO':({'REG':'gpio_rst_ctrl','FIELDS':({'FIELD_NAME':'gpio_cpu1x_rst', 'RST':1,'OFF':0},)},),
		'QSPI':({'REG':'qspi_rst_ctrl','FIELDS':({'FIELD_NAME':'qspi_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'qspi_cpu1x_rst', 'RST':1,'OFF':0} )},),
		'NAND':({'REG':'smc_rst_ctrl', 'FIELDS':({'FIELD_NAME':'smc_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'smc_cpu1x_rst', 'RST':1,'OFF':0} )},),
		'NOR': ({'REG':'smc_rst_ctrl', 'FIELDS':({'FIELD_NAME':'smc_ref_rst', 'RST':1,'OFF':0},
		{'FIELD_NAME':'smc_cpu1x_rst', 'RST':1,'OFF':0} )},),
		}

ezynq_uart.py

+16 −15

Original line number	Diff line number	Diff line
		@@ -119,22 +119,23 @@ class EzynqUART:
		def setup_uart(self,current_reg_sets,force=False,warn=False):

		uart_register_set=self.uart_register_set
		slcr_register_set=self.slcr_register_set
		slcr_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
		slcr_register_set.set_bitfields('uart_rst_ctrl',( # dflt=0
		('uart1_ref_rst', self.channel==1), # UART 1 reference clock domain reset: 0 - normal, 1 - reset
		('uart0_ref_rst', self.channel==0), # UART 0 reference clock domain reset: 0 - normal, 1 - reset
		('uart1_cpu1x_rst', self.channel==1), # UART 1 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		('uart0_cpu1x_rst', self.channel==0)),force,warn) #UART 0 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		slcr_register_set.flush()
		slcr_register_set.set_bitfields('uart_rst_ctrl',( # dflt=0
		('uart1_ref_rst', 0), # UART 1 reference clock domain reset: 0 - normal, 1 - reset
		('uart0_ref_rst', 0), # UART 0 reference clock domain reset: 0 - normal, 1 - reset
		('uart1_cpu1x_rst', 0), # UART 1 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		('uart0_cpu1x_rst', 0)),force,warn) #UART 0 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		reg_sets=slcr_register_set.get_register_sets(sort_addr=True,apply_new=True)

		uart_register_set.set_initial_state(reg_sets, True)# start from the current registers state
		# slcr_register_set=self.slcr_register_set
		# slcr_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
		# slcr_register_set.set_bitfields('uart_rst_ctrl',( # dflt=0
		# ('uart1_ref_rst', self.channel==1), # UART 1 reference clock domain reset: 0 - normal, 1 - reset
		# ('uart0_ref_rst', self.channel==0), # UART 0 reference clock domain reset: 0 - normal, 1 - reset
		# ('uart1_cpu1x_rst', self.channel==1), # UART 1 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		# ('uart0_cpu1x_rst', self.channel==0)),force,warn) #UART 0 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		# slcr_register_set.flush()
		# slcr_register_set.set_bitfields('uart_rst_ctrl',( # dflt=0
		# ('uart1_ref_rst', 0), # UART 1 reference clock domain reset: 0 - normal, 1 - reset
		# ('uart0_ref_rst', 0), # UART 0 reference clock domain reset: 0 - normal, 1 - reset
		# ('uart1_cpu1x_rst', 0), # UART 1 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		# ('uart0_cpu1x_rst', 0)),force,warn) #UART 0 CPU_1x clock domain (AMBA) reset: 0 - normal, 1 - reset
		# reg_sets=slcr_register_set.get_register_sets(sort_addr=True,apply_new=True)

		uart_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
		uart_register_set.set_bitfields('mode',( # dflt=4
		('chmode', 0), # Channel Mode: 0 - normal, 1 - auto echo, 2 - local loopback, 3 - remote loopback
		('nbstop', 0), # Number of stop bits: 0 - 1 stop bit, 1 - 1.5 stop bits, 2 - 2 stop bits, 3 - reserved

ezynq_uboot.py

+23 −40

Original line number	Diff line number	Diff line
		@@ -205,12 +205,21 @@ inline void register_setup(void)
		self._add_reg_writes(reg_sets)
		self.cfile+='}\n\n'

		def pll_setup (self, reg_sets,clk): #clk is an instance of ezynq_clk.EzynqClk
		def pll_setup (self, reg_sets):
		self.sections.append('pll_setup')
		self.cfile+='''/* Wait for PLLs locked:*/
		self.cfile+='''/* Wait for PLLs locked */
		inline void pll_setup(void)
		{
		\t/* Wait for all used PLLs locked, then release PLL bypass on each PLL */
		'''
		self._add_reg_writes(reg_sets)
		self.cfile+='}\n\n'

		def make_resets (self, reg_sets):
		self.sections.append('resets')
		self.cfile+='''/* Reset defined peripherals */
		inline void reset_peripherals(void)
		{
		'''
		self._add_reg_writes(reg_sets)
		self.cfile+='}\n\n'
		@@ -407,39 +416,21 @@ int arch_cpu_init(void)
		'''
		self._cp_led('LED_CHECKPOINT_3') # After setting clock registers

		self.cfile+='''/*
		Wait PLLs locked and turn off bypass - all clocks should have specified values now
		*/
		\tpll_setup();

		'''
		self.cfile+='\tpll_setup(); /* Wait PLLs locked and turn off bypass - all clocks should have specified values now */ \n'
		self.cfile+='\treset_peripherals(); /* Reset defined peripherals */\n'
		self._cp_led('LED_CHECKPOINT_4') # After PLL bypass is OFF
		if 'uart_init' in self.sections:
		self.cfile+='''/* Initialize UART for debug information output */
		\tuart_init();

		'''
		self.cfile+='\tuart_init(); /* Initialize UART for debug information output */\n'
		self._cp_led('LED_CHECKPOINT_5') # After UART is programmed

		if self.features.get_par_value_or_none('DUMP_SLCR_EARLY'):
		self.cfile+='\tuart_puts("SLCR registers before DCI/DDR initialization\\r\\n");\n'
		self.cfile+='\tdump_slcr_regs(); /* Dump all SLCR registers before DCI/DDR initialization */\n'
		if self.features.get_par_value_or_none('DUMP_DDRC_EARLY'):
		self.cfile+='\tuart_puts("DDRC registers before DCI/DDR initialization\\r\\n");\n'
		self.cfile+='\tdump_ddrc_regs(); /* Dump all DDRC registers before DCI/DDR initialization */\n'
		self.cfile+='''/*
		Calibrate DDR DCI impedance and wait for completion
		*/
		\tdci_calibration();

		'''
		self.cfile+='\tdci_calibration(); /* Calibrate DDR DCI impedance and wait for completion */\n'
		self._cp_led('LED_CHECKPOINT_6') # After DCI is calibrated
		self.cfile+='''/*
		Remove soft reset from DDR controller - that starts initialization. Wait for completion
		*/
		\tddr_start();

		'''
		self.cfile+='\tddr_start(); /* Remove soft reset from DDR controller - this will start initialization. Wait for completion */\n'
		self._cp_led('LED_CHECKPOINT_7') # After DDR is initialized
		if self.features.get_par_value_or_none('DUMP_SLCR_LATE'):
		self.cfile+='\tuart_puts("SLCR registers after DCI/DDR initialization\\r\\n");\n'
		@@ -447,13 +438,10 @@ int arch_cpu_init(void)
		if self.features.get_par_value_or_none('DUMP_DDRC_LATE'):
		self.cfile+='\tuart_puts("DDRC registers after DCI/DDR initialization\\r\\n");\n'
		self.cfile+='\tdump_ddrc_regs(); /* Dump all DDRC registers after DCI/DDR initialization */\n'
		self.cfile+='''/*
		Copy 3 pages of OCM from 0x00000.0x2ffff to DDR 0x4000000.0x402ffff
		*/
		self.cfile+='''/* Copy 3 pages of OCM from 0x00000.0x2ffff to DDR 0x4000000.0x402ffff*/
		\tint * s= (int *) 0;
		\tint * d= (int *) 0x4000000;
		\twhile (s< ((int )0x30000)) d++=*s++;

		'''
		self.cfile+='\tddrc_wait_queue_empty(); /* Wait no commands are pending in DDRC queue */\n'

		@@ -469,13 +457,8 @@ int arch_cpu_init(void)
		# seems some delay is needed before remapping DDR memory
		self.cfile+='\tddrc_wait_queue_empty(); /* seems some delay is needed here before remapping DDR memory */\n'
		self._cp_led('LED_CHECKPOINT_9') # After relocation to DDR (to 0x4000000+ )
		self.cfile+='''/*
		Remap DDR to zero, FILTERSTART
		*/
		\twritel(0, &scu_base->filter_start);
		/*
		Device config APB, unlock the PCAP
		*/
		self.cfile+='\twritel(0, &scu_base->filter_start); /* Remap DDR to zero, FILTERSTART */\n'
		self.cfile+='''/* Device config APB, unlock the PCAP */
		\twritel(0x757BDF0D, &devcfg_base->unlock);
		\twritel(0xFFFFFFFF, &devcfg_base->rom_shadow);
		'''

ezynqcfg.py

+8 −10

Original line number	Diff line number	Diff line
		@@ -361,6 +361,10 @@ segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'CLK','TITLE':'Clock regi
		#print 'Debug mode: CLK/PLL configuration by u-boot'
		reg_sets=clk.clocks_pll_bypass_off(reg_sets,force)
		segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'PLL','TITLE':'Registers to switch to PLL'})

		reg_sets=clk.reset_peripherals(reg_sets,force)
		segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'RESETS','TITLE':'Resetting defined peripherals after clocks changed'})

		if u_boot.features.get_par_value_or_none('BOOT_DEBUG'):
		uart=ezynq_uart.EzynqUART()
		uart.parse_parameters(raw_configs,used_mio_interfaces,False)
		@@ -490,15 +494,6 @@ if args.outfile:
		print 'Generating binary output ',os.path.abspath(args.outfile)
		write_image(image,args.outfile)
		if (args.lowlevel):
		# segments.append({'TO':len(reg_sets),'RBL':True,'NAME':'MIO','TITLE':'MIO registers configuration'})
		# segments.append({'TO':len(reg_sets),'RBL':True,'NAME':'DDR0','TITLE':'DDR registers configuration'})

		# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'CLK','TITLE':'Clock registers configuration'})
		# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'PLL','TITLE':'Registers to switch to PLL'})
		# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'UART_INIT','TITLE':'Registers to initialize UART'})
		# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DCI','TITLE':'DDR DCI Calibration'})
		# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'})
		#CONFIG_EZYNQ_UART_DEBUG_USE_LED
		if 'SLCR_LOCK_UNLOCK' in segment_dict:
		u_boot.make_slcr_lock_unlock (reg_sets[segment_dict['SLCR_LOCK_UNLOCK']['FROM']:segment_dict['SLCR_LOCK_UNLOCK']['TO']])
		if 'LED' in segment_dict:
		@@ -507,7 +502,10 @@ if (args.lowlevel):
		if 'CLK' in segment_dict:
		u_boot.registers_setup (reg_sets[segment_dict['CLK']['FROM']:segment_dict['CLK']['TO']],clk,num_rbl_regs)
		if 'PLL' in segment_dict:
		u_boot.pll_setup (reg_sets[segment_dict['PLL']['FROM']:segment_dict['PLL']['TO']],clk)
		u_boot.pll_setup (reg_sets[segment_dict['PLL']['FROM']:segment_dict['PLL']['TO']])
		if 'RESETS' in segment_dict:
		u_boot.make_resets (reg_sets[segment_dict['RESETS']['FROM']:segment_dict['RESETS']['TO']])

		if 'UART_INIT' in segment_dict:
		u_boot.uart_init (reg_sets[segment_dict['UART_INIT']['FROM']:segment_dict['UART_INIT']['TO']])
		if 'UART_XMIT' in segment_dict:

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