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ezynq
Commit 435a11b3 authored by Andrey Filippov's avatar Andrey Filippov
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Adding support for elphel393, new configurations, bug fixes

parent b2b3c812
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Showing with 1204 additions and 114 deletions
ezynq_ddr.py
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......@@ -45,6 +45,7 @@ class EzynqDDR:
self.features=ezynq_feature_config.EzynqFeatures(self.DDR_CFG_DEFS,0) #DDR_CFG_DEFS
self.ddrc_register_set= ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits)
self.ddriob_register_set=ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits)
def generate_command_queue_empty(self):
# generate code to be included in u-boot for testing DDR command queue
......@@ -58,6 +59,17 @@ class EzynqDDR:
self.features.parse_features(raw_configs)
def check_missing_features(self):
self.features.check_missing_features()
if (self.features.get_par_value('SILICON')=='1'):
self.silicon=1
elif (self.features.get_par_value('SILICON')=='2'):
self.silicon=2
elif (self.features.get_par_value('SILICON')=='3'):
self.silicon=3
elif (self.features.get_par_value('SILICON')=='3.1'):
self.silicon=3
else:
self.silicon=3
def html_list_features(self,html_file):
if not html_file:
return
......@@ -402,6 +414,7 @@ class EzynqDDR:
('reg_ddrc_pad_pd', padPD), # 0x0
('reg_ddrc_t_xp', XP), # 0x4
('reg_ddrc_wr2rd', WR2RD), # 0xe
# ('reg_ddrc_wr2rd', WR2RD | 0x10), # TODO: REMOVE !!!!
('reg_ddrc_rd2wr', RD2WR), # 0x7
('reg_ddrc_write_latency', write_latency)),force,warn) #5
# reg DRAM_param_reg3, 0x270872d0 , 0x272872d0, 0x272872d0 (first time reg_ddrc_sdram is not set, the rest is the same)
......@@ -420,7 +433,7 @@ class EzynqDDR:
('reg_ddrc_read_latency', RL), #7
('reg_ddrc_en_dfi_dram_clk_disable',en_dfi_dram_clk_disable), #0
('reg_ddrc_mobile', (0,1)[is_LPDDR2]), # 0
('reg_ddrc_sdram', 1), # Shown reserved/default==0, but actually is set to 1 (2 and 3-rd time)
('reg_ddrc_sdram', (1,0)[self.silicon==3] ), # Shown reserved/default==0, but actually is set to 1 (2 and 3-rd time)
('reg_ddrc_refresh_to_x32', ddrc_refresh_to_x32), # 8
('reg_ddrc_t_rp', RP), # 7
('reg_ddrc_refresh_margin', refresh_margin), # 2
......@@ -429,8 +442,9 @@ class EzynqDDR:
# reg DRAM_param_reg4, 0, 0x3c, 0x3c
ddrc_register_set.set_word ('dram_param_reg4',0x0,force) # reset all fields. This register is controlled by the hardware during automatic initialization
#Maybe just the LSBB (reg_ddrc_en_2t_timing_mode) is needed for "2t timing mode" - is it non-common?
ddrc_register_set.set_bitfields('dram_param_reg4',(('reg_ddrc_max_rank_rd', 0xf)),force,warn) # Not documented, but appears to be set in 2-nd and 3-rd round
ddrc_register_set.set_bitfields('dram_param_reg4',(('reg_ddrc_max_rank_rd', (0xf,0)[self.silicon==3])),force,warn) # Not documented, but appears to be set in 2-nd and 3-rd round
# reg DRAM_init_param, 0x2007 always (default)
MRD = self.features.get_par_value('CCD')
......@@ -439,6 +453,8 @@ class EzynqDDR:
ddrc_register_set.set_bitfields('dram_init_param',(('reg_ddrc_t_mrd', MRD), # 0x4
('reg_ddrc_pre_ocd_x32', pre_ocd_x32), # 0x0
('reg_ddrc_final_wait_x32', final_wait_x32)),force,warn) # 0x7
# reg DRAM_emr_reg, 0x8 always (default)
# ddrc_register_set.set_word ('dram_emr_reg', 0x8, force)
emr3=0 # Only 3 LSBs are used by DDR and should be set to 0 - correct values will be set by the DDRC
......@@ -612,7 +628,11 @@ class EzynqDDR:
#
if is_DDR3:
t_post_cke=400.0
t_pre_cke= 200000.0
# t_pre_cke= 200000.0
t_pre_cke= 500000.0 # as generated by Vivado 2013.3, maybe same applies to other DDRx
#TODO: REMOVE !!!!
# t_pre_cke= 200000.0 # as generated by Vivado 2013.3, maybe same applies to other DDRx
elif is_DDR2:
t_post_cke=400.0
t_pre_cke= 200000.0
......@@ -684,9 +704,9 @@ class EzynqDDR:
# reg DRAM_odt_reg, 0x3c000, 0x3c248,0x3c248
# Could not find documentation, default value may work (first time 3 default/do not change values were different
rank0_wr_odt = 1 # default, was 0 first time
rank1_rd_odt = 1 # default, was 0 first time
rank1_wr_odt = 1 # default, was 0 first time
rank0_wr_odt = (1,0)[self.silicon==3] # default, was 0 first time
rank1_rd_odt = (1,0)[self.silicon==3] # default, was 0 first time
rank1_wr_odt = (1,0)[self.silicon==3] # default, was 0 first time
wr_local_odt = 3 # default
idle_local_odt= 3 # default
......@@ -726,8 +746,8 @@ class EzynqDDR:
),force,warn)
# reg DLL_calib, 0x0, then 2 times 0x101 (default). Does it need to be 0 before training. Not listed in 10-11 - probably can be skipped during init
dis_dll_calib = 0 # if 1 - disable automatic periodic DLL correction
dll_calib_to_max_x1024 = 1 # reserved, do not modify
dll_calib_to_min_x1024 = 1 # reserved, do not modify
dll_calib_to_max_x1024 = (1,0)[self.silicon==3] # reserved, do not modify
dll_calib_to_min_x1024 = (1,0)[self.silicon==3] # reserved, do not modify
ddrc_register_set.set_bitfields('dll_calib',(('reg_ddrc_dis_dll_calib', dis_dll_calib), # 0
('reg_ddrc_dll_calib_to_max_x1024', dll_calib_to_max_x1024), # 1
('reg_ddrc_dll_calib_to_min_x1024', dll_calib_to_min_x1024) # 1
......@@ -772,7 +792,7 @@ class EzynqDDR:
),force,warn)
# reg ctrl_reg3 0x284141 - all 3 times (non-default, default=0x00284027)
if is_DDR3: # other - N/A
dfi_t_wlmrd= int(math.ceil(self.features.get_par_value('T_WLMRD')/tCK))
dfi_t_wlmrd= self.features.get_par_value('WLMRD')
rdlvl_rr = 0x41 # default = 0x40 (Did not understand how to calculate, using actual for DDR3)
ddrc_register_set.set_bitfields('ctrl_reg3',(('reg_ddrc_dfi_t_wlmrd', dfi_t_wlmrd),
('reg_ddrc_rdlvl_rr', rdlvl_rr)),force,warn) # 0x28 DDR3 only: tWLMRD from DRAM specs
......@@ -863,12 +883,17 @@ class EzynqDDR:
),force,warn)
# reg reg_2c dflt=0 act=0xffffff
# use_rd_data_eye_level = (0,1)[self.features.get_par_value('TRAIN_DATA_EYE')]
# use_rd_dqs_gate_level = (0,1)[self.features.get_par_value('TRAIN_READ_GATE')]
# use_wr_level = (0,1)[self.features.get_par_value('TRAIN_WRITE_LEVEL')]
dfi_rdlvl_max_x1024=0xfff # using actual/recommended
dfi_wrlvl_max_x1024=0xfff # using actual/recommended
#Vivado 2013.3 set DFI training to 1
ddrc_register_set.set_bitfields('reg_2c',(
('reg_ddrc_dfi_rd_data_eye_train', 0), # 0 DDR3 and LPDDR2 only: 1 - read data eye training (part of init sequence)
('reg_ddrc_dfi_rd_dqs_gate_level', 0), # 0 1 - Read DQS gate leveling mode (DDR3 DFI only)
('reg_ddrc_dfi_wr_level_en', 0), # 0 1 - Write leveling mode (DDR3 DFI only)
('reg_ddrc_dfi_rd_data_eye_train', use_rd_data_eye_level), # 0 DDR3 and LPDDR2 only: 1 - read data eye training (part of init sequence)
('reg_ddrc_dfi_rd_dqs_gate_level', use_rd_dqs_gate_level), # 0 1 - Read DQS gate leveling mode (DDR3 DFI only)
('reg_ddrc_dfi_wr_level_en', use_wr_level), # 0 1 - Write leveling mode (DDR3 DFI only)
('ddrc_reg_trdlvl_max_error', 0), # 0 READONLY: DDR3 and LPDDR2 only: leveling/gate training timeout (clear on write)
('ddrc_reg_twrlvl_max_error', 0), # 0 READONLY: DDR3 only: write leveling timeout (clear on write)
('dfi_rdlvl_max_x1024',dfi_rdlvl_max_x1024), # 0xfff Read leveling maximal time in 1024 clk. Typical value 0xFFF
......@@ -898,6 +923,11 @@ class EzynqDDR:
programECC = True
if programECC:
# reg che_ecc_control_reg_offset (offs=0xc4) : 0 - always, ==dflt
ddrc_register_set.set_bitfields('che_ecc_control_reg_offset',(
('clear_correctable_dram_ecc_error', 1), # 0 1 - clear correctable log (valid+counters)
('clear_uncorrectable_dram_ecc_error', 1), # 0 1 - clear uncorrectable log (valid+counters)
),force,warn)
ddrc_register_set.flush()
ddrc_register_set.set_bitfields('che_ecc_control_reg_offset',(
('clear_correctable_dram_ecc_error', 0), # 0 1 - clear correctable log (valid+counters)
('clear_uncorrectable_dram_ecc_error', 0), # 0 1 - clear uncorrectable log (valid+counters)
......@@ -1031,82 +1061,102 @@ class EzynqDDR:
('reg_phy_rdlvl_inc_mode', 0), #
('reg_phy_data_slice_in_use',slice_in_use3), # 1 Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 3 is valid (always 1)
),force,warn)
gatelvl_init_ratio0=self.features.get_par_value('PHY_GTLV_INIT_RATIO_0')
gatelvl_init_ratio1=self.features.get_par_value('PHY_GTLV_INIT_RATIO_1')
gatelvl_init_ratio2=self.features.get_par_value('PHY_GTLV_INIT_RATIO_2')
gatelvl_init_ratio3=self.features.get_par_value('PHY_GTLV_INIT_RATIO_3')
wrlvl_init_ratio0=self.features.get_par_value('PHY_WRLV_INIT_RATIO_0')
wrlvl_init_ratio1=self.features.get_par_value('PHY_WRLV_INIT_RATIO_1')
wrlvl_init_ratio2=self.features.get_par_value('PHY_WRLV_INIT_RATIO_2')
wrlvl_init_ratio3=self.features.get_par_value('PHY_WRLV_INIT_RATIO_3')
# reg phy_init_ratio0, offs=0x12C dflt:0x0 actual: 0x0
ddrc_register_set.set_bitfields('phy_init_ratio0',( # PHY init ratio register for data slice 0
('reg_phy_gatelvl_init_ratio', 0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 0
('reg_phy_wrlvl_init_ratio', 0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 0
('reg_phy_gatelvl_init_ratio', gatelvl_init_ratio0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 0
('reg_phy_wrlvl_init_ratio', wrlvl_init_ratio0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 0
),force,warn)
# reg phy_init_ratio1, offs=0x130 dflt:0x0 actual: 0x0
ddrc_register_set.set_bitfields('phy_init_ratio1',( # PHY init ratio register for data slice 1
('reg_phy_gatelvl_init_ratio', 0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 1
('reg_phy_wrlvl_init_ratio', 0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 1
('reg_phy_gatelvl_init_ratio', gatelvl_init_ratio1), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 1
('reg_phy_wrlvl_init_ratio', wrlvl_init_ratio1), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 1
),force,warn)
# reg phy_init_ratio2, offs=0x134 dflt:0x0 actual: 0x0
ddrc_register_set.set_bitfields('phy_init_ratio2',( # PHY init ratio register for data slice 2
('reg_phy_gatelvl_init_ratio', 0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 2
('reg_phy_wrlvl_init_ratio', 0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 2
('reg_phy_gatelvl_init_ratio', gatelvl_init_ratio2), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 2
('reg_phy_wrlvl_init_ratio', wrlvl_init_ratio2), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 2
),force,warn)
# reg phy_init_ratio3, offs=0x138 dflt:0x0 actual: 0x0
ddrc_register_set.set_bitfields('phy_init_ratio3',( # PHY init ratio register for data slice 3
('reg_phy_gatelvl_init_ratio', 0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 3
('reg_phy_wrlvl_init_ratio', 0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 3
('reg_phy_gatelvl_init_ratio', gatelvl_init_ratio3), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 3
('reg_phy_wrlvl_init_ratio', wrlvl_init_ratio3), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 3
),force,warn)
dqs_slave_ratio0=0x35 # default=40
dqs_slave_ratio1=0x35 # default=40
dqs_slave_ratio2=0x35 # default=40
dqs_slave_ratio3=0x35 # default=40
rd_dqs_slave_ratio0=0x35 # default=40
rd_dqs_slave_ratio1=0x35 # default=40
rd_dqs_slave_ratio2=0x35 # default=40
rd_dqs_slave_ratio3=0x35 # default=40
# reg phy_rd_dqs_cfg0, offs=0x140 dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg0',( # PHY read DQS configuration register for data slice 0
('reg_phy_rd_dqs_slave_delay', 0), # 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 0
('reg_phy_rd_dqs_slave_force', 0), # 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 0
('reg_phy_rd_dqs_slave_ratio', dqs_slave_ratio0), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 0
('reg_phy_rd_dqs_slave_ratio', rd_dqs_slave_ratio0), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 0
),force,warn)
# reg phy_rd_dqs_cfg1, offs=0x144 dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg1',( # PHY read DQS configuration register for data slice 1
('reg_phy_rd_dqs_slave_delay', 0), # 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 1
('reg_phy_rd_dqs_slave_force', 0), # 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 1
('reg_phy_rd_dqs_slave_ratio', dqs_slave_ratio1), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 1
('reg_phy_rd_dqs_slave_ratio', rd_dqs_slave_ratio1), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 1
),force,warn)
# reg phy_rd_dqs_cfg2, offs=0x148 dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg2',( # PHY read DQS configuration register for data slice 2
('reg_phy_rd_dqs_slave_delay', 0), # 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 2
('reg_phy_rd_dqs_slave_force', 0), # 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 2
('reg_phy_rd_dqs_slave_ratio', dqs_slave_ratio2), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 2
('reg_phy_rd_dqs_slave_ratio', rd_dqs_slave_ratio2), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 2
),force,warn)
# reg phy_rd_dqs_cfg3, offs=0x14c dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg3',( # PHY read DQS configuration register for data slice 3
('reg_phy_rd_dqs_slave_delay', 0), # 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 3
('reg_phy_rd_dqs_slave_force', 0), # 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 3
('reg_phy_rd_dqs_slave_ratio', dqs_slave_ratio3), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 3
('reg_phy_rd_dqs_slave_ratio', rd_dqs_slave_ratio3), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 3
),force,warn)
wr_dqs_slave_ratio0=self.features.get_par_value('PHY_WR_DQS_SLAVE_RATIO_0')
wr_dqs_slave_ratio1=self.features.get_par_value('PHY_WR_DQS_SLAVE_RATIO_1')
wr_dqs_slave_ratio2=self.features.get_par_value('PHY_WR_DQS_SLAVE_RATIO_2')
wr_dqs_slave_ratio3=self.features.get_par_value('PHY_WR_DQS_SLAVE_RATIO_3')
# reg phy_wr_dqs_cfg0, offs=0x154 dflt:0 actual: 0
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg0',( # ,PHY write DQS configuration register for data slice 0
('reg_phy_wr_dqs_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 0
('reg_phy_wr_dqs_slave_force', 0), # 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 0
('reg_phy_wr_dqs_slave_ratio', 0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 0. Program manual training ratio
('reg_phy_wr_dqs_slave_ratio', wr_dqs_slave_ratio0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 0. Program manual training ratio
),force,warn)
# reg phy_wr_dqs_cfg0, offs=0x158 dflt:0 actual: 0
# reg phy_wr_dqs_cfg1, offs=0x158 dflt:0 actual: 0
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg1',( # ,PHY write DQS configuration register for data slice 1
('reg_phy_wr_dqs_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 1
('reg_phy_wr_dqs_slave_force', 0), # 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 1
('reg_phy_wr_dqs_slave_ratio', 0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 1. Program manual training ratio
('reg_phy_wr_dqs_slave_ratio', wr_dqs_slave_ratio1), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 1. Program manual training ratio
),force,warn)
# reg phy_wr_dqs_cfg0, offs=0x15c dflt:0 actual: 0
# reg phy_wr_dqs_cfg2, offs=0x15c dflt:0 actual: 0
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg2',( # ,PHY write DQS configuration register for data slice 2
('reg_phy_wr_dqs_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 2
('reg_phy_wr_dqs_slave_force', 0), # 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 2
('reg_phy_wr_dqs_slave_ratio', 0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 2. Program manual training ratio
('reg_phy_wr_dqs_slave_ratio', wr_dqs_slave_ratio2), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 2. Program manual training ratio
),force,warn)
# reg phy_wr_dqs_cfg0, offs=0x160 dflt:0 actual: 0
# reg phy_wr_dqs_cfg3, offs=0x160 dflt:0 actual: 0
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg3',( # ,PHY write DQS configuration register for data slice 3
('reg_phy_wr_dqs_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 3
('reg_phy_wr_dqs_slave_force', 0), # 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 3
('reg_phy_wr_dqs_slave_ratio', 0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 3. Program manual training ratio
('reg_phy_wr_dqs_slave_ratio', wr_dqs_slave_ratio3), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 3. Program manual training ratio
),force,warn)
fifo_we_slave_ratio0=0x35 # default=40
fifo_we_slave_ratio1=0x35 # default=40
fifo_we_slave_ratio2=0x35 # default=40
fifo_we_slave_ratio3=0x35 # default=40
fifo_we_slave_ratio0=self.features.get_par_value('PHY_FIFO_WE_SLAVE_RATIO_0')
fifo_we_slave_ratio1=self.features.get_par_value('PHY_FIFO_WE_SLAVE_RATIO_1')
fifo_we_slave_ratio2=self.features.get_par_value('PHY_FIFO_WE_SLAVE_RATIO_2')
fifo_we_slave_ratio3=self.features.get_par_value('PHY_FIFO_WE_SLAVE_RATIO_3')
# reg phy_we_cfg0, offs=0x168 dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_we_cfg0',( # PHY FIFO write enable configuration register for data slice 0
......@@ -1132,10 +1182,10 @@ class EzynqDDR:
('reg_phy_fifo_we_in_force', 0), # 0 0 - use reg_phy_fifo_we_slave_ratio for fifo_we_0 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 3
('reg_phy_fifo_we_slave_ratio',fifo_we_slave_ratio3), # 0x35 Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 3. Program manual training ratio
),force,warn)
wr_data_slave_ratio0=0x40
wr_data_slave_ratio1=0x40
wr_data_slave_ratio2=0x40
wr_data_slave_ratio3=0x40
wr_data_slave_ratio0=self.features.get_par_value('PHY_WR_DATA_SLAVE_RATIO_0')
wr_data_slave_ratio1=self.features.get_par_value('PHY_WR_DATA_SLAVE_RATIO_1')
wr_data_slave_ratio2=self.features.get_par_value('PHY_WR_DATA_SLAVE_RATIO_2')
wr_data_slave_ratio3=self.features.get_par_value('PHY_WR_DATA_SLAVE_RATIO_3')
# reg wr_data_slv0, offs=0x17c dflt:0x80 actual: 0x40
ddrc_register_set.set_bitfields('wr_data_slv0',( # PHY write data slave ratio configuration register for data slice 0
('reg_phy_wr_data_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 0
......@@ -1161,10 +1211,16 @@ class EzynqDDR:
('reg_phy_wr_data_slave_ratio',wr_data_slave_ratio3), # 0x40 Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 3. Program manual training ratio
),force,warn)
# reg reg_64, offs=0x190 dflt:0x10020000 actual:0x20000(first time)-0x10020000-0x10020000
use_rank0_delays = 1 # marked as reserved, but actually is first set to 0 - maybe not needed
use_rank0_delays = (1,0)[self.silicon==3] # marked as reserved, but actually is first set to 0 - maybe not needed
phy_lpddr= (0,1)[is_LPDDR2]
ctrl_slave_ratio=0x80 # defualt/actual
phy_ctrl_slave_ratio=self.features.get_par_value('PHY_CTRL_SLAVE_RATIO') # 0x80 # default/actual
sel_logic = 0 # Read leveling algorithm select - 0:algorithm 1, 1: algorithm 2
phy_invert_clkout=self.features.get_par_value('PHY_INVERT_CLK')
#define CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO 0x100 /* Ratio for address/command (256 - clock period) */
#define CONFIG_EZYNQ_PHY_INVERT_CLK /* RInvert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
ddrc_register_set.set_bitfields('reg_64',( # Training control 2
('reg_phy_int_lpbk', 0), # reserved
('reg_phy_cmd_latency', 0), # 1: Delay command to PHY by a FF
......@@ -1172,10 +1228,10 @@ class EzynqDDR:
('reg_phy_use_rank0_delays', use_rank0_delays), # reserved
('reg_phy_ctrl_slave_delay', 0), # when reg_phy_rd_dqs_slave_force==1 this value (combined with bits 18:19 of reg_65) set address/command slave DLL
('reg_phy_ctrl_slave_force', 0), # 0:use reg_phy_ctrl_slave_ratio for addr/cmd slave DLL, 1 - overwrite with reg_phy_ctrl_slave_delay
('reg_phy_ctrl_slave_ratio',ctrl_slave_ratio), # address/command delay in clock/256
('reg_phy_ctrl_slave_ratio',phy_ctrl_slave_ratio), # address/command delay in clock/256
('reg_phy_sel_logic', sel_logic), # Read leveling algorithm select - 0:algorithm 1, 1: algorithm 2
('reg_phy_all_dq_mpr_rd_resp',0), # reserved
('reg_phy_invert_clkout', 0), # 1 - invert clock polarity to DRAM
('reg_phy_invert_clkout', phy_invert_clkout), # 1 - invert clock polarity to DRAM
('reg_phy_bist_mode', 0), # reserved
('reg_phy_bist_force_err', 0), # reserved
('reg_phy_bist_enable', 0), # reserved
......@@ -1215,7 +1271,7 @@ class EzynqDDR:
arb_pri_wr_port3=0x3ff # lowest
# reg axi_priority_wr_port0, offs=0x208 dflt:0x803FF actual: 0x803ff
ddrc_register_set.set_bitfields('axi_priority_wr_port0',( # AXI priority control for write port 0
('reserved1', 0x1), # 0x1
('reserved1', (1,0)[self.silicon==3]), # 0x1
('reg_arb_dis_page_match_wr_portn', 0), # Disable page match feature
('reg_arb_disable_urgent_wr_portn', 0), # Disable urgent for this Write Port
('reg_arb_disable_aging_wr_portn', 0), # Disable aging for this Write Port
......@@ -1226,7 +1282,7 @@ class EzynqDDR:
# reg axi_priority_wr_port1, offs=0x20c dflt:0x803FF actual: 0x803ff
ddrc_register_set.set_bitfields('axi_priority_wr_port1',( # AXI priority control for write port 1
('reserved1', 0x1), # 0x1
('reserved1', 0x1), # 0x1
('reserved1', (1,0)[self.silicon==3]), # 0x1
('reg_arb_dis_page_match_wr_portn', 0), # Disable page match feature
('reg_arb_disable_urgent_wr_portn', 0), # Disable urgent for this Write Port
('reg_arb_disable_aging_wr_portn', 0), # Disable aging for this Write Port
......@@ -1235,7 +1291,7 @@ class EzynqDDR:
),force,warn)
# reg axi_priority_wr_port2, offs=0x210 dflt:0x803FF actual: 0x803ff
ddrc_register_set.set_bitfields('axi_priority_wr_port2',( # AXI priority control for write port 2
('reserved1', 0x1), # 0x1
('reserved1', (1,0)[self.silicon==3]), # 0x1
('reg_arb_dis_page_match_wr_portn', 0), # Disable page match feature
('reg_arb_disable_urgent_wr_portn', 0), # Disable urgent for this Write Port
('reg_arb_disable_aging_wr_portn', 0), # Disable aging for this Write Port
......@@ -1244,7 +1300,7 @@ class EzynqDDR:
),force,warn)
# reg axi_priority_wr_port3, offs=0x214 dflt:0x803FF actual: 0x803ff
ddrc_register_set.set_bitfields('axi_priority_wr_port3',( # AXI priority control for write port 3
('reserved1', 0x1), # 0x1
('reserved1', (1,0)[self.silicon==3]), # 0x1
('reg_arb_dis_page_match_wr_portn', 0), # Disable page match feature
('reg_arb_disable_urgent_wr_portn', 0), # Disable urgent for this Write Port
('reg_arb_disable_aging_wr_portn', 0), # Disable aging for this Write Port
......@@ -1343,11 +1399,14 @@ class EzynqDDR:
ddriob_register_set.flush()# close previous register settings
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
('enable',1),
('vrn_out',(1,0)[self.silicon==3]),
('nref_opt1',0),
('nref_opt2',0),
('nref_opt4',1),
('pref_opt2',0),
('update_control',0)),force,warn)
ddriob_register_set.flush()# close previous register settings
# add wait for DCI calibration DONE
ddriob_register_set.wait_reg_field_values('ddriob_dci_status',('done',1), True, warn)
......
ezynq_ddrc_defs.py
View file @ 435a11b3
......@@ -72,7 +72,7 @@ DDRC_DEFS={ #not all fields are defined currently
'reg_ddrc_rd2pre': {'r':(23,27),'d': 0x6,'c':'Read to precharge in the same bank'}, #0x4
'reg_ddrc_pad_pd': {'r':(20,22),'d': 0x0,'c':'non-DFI only: pads in/out powersave, in clocks'}, #0x0
'reg_ddrc_t_xp': {'r':(15,19),'d': 0x2,'c':'tXP - power down exit to any operation'}, #0x4
'reg_ddrc_wr2rd': {'r':(10,13),'d': 0x16,'c':'tWTR - write -to -read (clocks)'}, #0xe
'reg_ddrc_wr2rd': {'r':(10,14),'d': 0x16,'c':'tWTR - write -to -read (clocks)'}, #0xe
'reg_ddrc_rd2wr': {'r':( 5, 9),'d': 0x8,'c':'tRTW - read -to -write (clocks)'}, #0x7
'reg_ddrc_write_latency': {'r':( 0, 4),'d': 0x4,'c':'one clock less than actual DDR write latency'}}}, #0x5
'dram_param_reg3': {'OFFS': 0x020,'DFLT':0x250882D0,'RW':'M','FIELDS':{ #272872d0
......@@ -82,7 +82,7 @@ DDRC_DEFS={ #not all fields are defined currently
'reg_ddrc_read_latency': {'r':(24,28),'d': 0x5,'c':'Read Latency, clocks'}, # 0x7
'reg_ddrc_en_dfi_dram_clk_disable': {'r':(23,23),'d': 0,'c':'Enables clock disable...'},
'reg_ddrc_mobile': {'r':(22,22),'d': 0,'c':'0 - DDR2/DDR3, 1 - LPDDR2'},
'reg_ddrc_sdram': {'r':(21,21),'d': 0,'c':'reserved'}, # 0x1
'reg_ddrc_sdram': {'r':(21,21),'d': 0,'c':'silicon 1,2: 1 - SDRAM, 0 - non-SDRAM. Silicon 3: 0'},# 0x1
'reg_ddrc_refresh_to_x32': {'r':(16,20),'d': 0x8,'c':'Dynamic, "speculative refresh"'},
'reg_ddrc_t_rp': {'r':(12,15),'d': 0x8,'c':'tRP'}, # 0x7
'reg_ddrc_refresh_margin': {'r':( 8,11),'d': 0x2,'c':'do refresh this cycles before timer expires'},
......@@ -152,17 +152,17 @@ DDRC_DEFS={ #not all fields are defined currently
'reg_ddrc_addrmap_row_b0': {'r':( 0, 3),'d':0x5,'c':'Selects address bits for row. addr. bit 0, Valid 0..11, int. base=9'}}}, # 0x6
'dram_odt_reg': {'OFFS': 0x048,'DFLT':0x00000249,'RW':'RW','FIELDS':{ # 0x3c248
'reg_ddrc_rank3_wr_odt': {'r':(29,27),'d':0,'c':'reserved'},
'reg_ddrc_rank3_wr_odt': {'r':(29,27),'d':0,'c':'reserved'},
'reg_ddrc_rank3_rd_odt': {'r':(24,26),'d':0,'c':'reserved'},
'reg_ddrc_rank2_wr_odt': {'r':(21,23),'d':0,'c':'reserved'},
'reg_ddrc_rank2_rd_odt': {'r':(18,20),'d':0,'c':'reserved'},
'reg_phy_idle_local_odt': {'r':(16,17),'d':0,'c':'2-bit drive ODT when OE is inactive and no read (power save)'}, # 0x3
'reg_phy_wr_local_odt': {'r':(14,15),'d':0,'c':'ODT strength during write leveling'}, #0x3
'reg_phy_rd_local_odt': {'r':(12,13),'d':0,'c':'ODT strength during read'},
'reg_ddrc_rank1_wr_odt': {'r':( 9,11),'d':0x1,'c':'reserved'},
'reg_ddrc_rank1_rd_odt': {'r':( 6, 8),'d':0x1,'c':'reserved'},
'reg_ddrc_rank0_wr_odt': {'r':( 3, 5),'d':0x1,'c':'reserved'},
'reg_ddrc_rank0_rd_odt': {'r':( 0, 2),'d':0x1,'c':'reserved'}}}, # 0x0
'reg_ddrc_rank1_wr_odt': {'r':( 9,11),'d':0x1,'c':'reserved, unused in silicon 3'},
'reg_ddrc_rank1_rd_odt': {'r':( 6, 8),'d':0x1,'c':'reserved, unused in silicon 3'},
'reg_ddrc_rank0_wr_odt': {'r':( 3, 5),'d':0x1,'c':'reserved, unused in silicon 3'},
'reg_ddrc_rank0_rd_odt': {'r':( 0, 2),'d':0x0,'c':'reserved, unused in silicon 3'}}}, # 0x0
'phy_dbg_reg': {'OFFS': 0x04C,'DFLT':0x00000000,'RW':'R','FIELDS':{
'phy_reg_bc_fifo_re3': {'r':(19,19),'d':0,'m':'R','c':'Debug read capture FIFO read enable for data slice 3'},
'phy_reg_bc_fifo_we3': {'r':(18,18),'d':0,'m':'R','c':'Debug read capture FIFO write enable for data slice 3'},
......@@ -202,8 +202,8 @@ DDRC_DEFS={ #not all fields are defined currently
'ddrc_reg_operating_mode': {'r':( 0, 2),'d':0,'m':'R','c':'DDRC init, 1 - normal, 2 - power down, 3 - self refresh, >=4 - deep power down LPDDR2'}}},
'dll_calib': {'OFFS': 0x058,'DFLT':0x00000101,'RW':'RW','FIELDS':{ # 0x101
'reg_ddrc_dis_dll_calib': {'r':(16,16),'d':0,'c':'Dynamic: 1- disable DLL_calib, 0 - issue DLL_calib periodically'},
'reg_ddrc_dll_calib_to_max_x1024': {'r':( 8,15),'d':0x1,'c':'reserved'},
'reg_ddrc_dll_calib_to_min_x1024': {'r':( 0, 7),'d':0x1,'c':'reserved'}}},
'reg_ddrc_dll_calib_to_max_x1024': {'r':( 8,15),'d':0x1,'c':'reserved, unused in silicon 3'},
'reg_ddrc_dll_calib_to_min_x1024': {'r':( 0, 7),'d':0x1,'c':'reserved, unused in silicon 3'}}},
'odt_delay_hold': {'OFFS': 0x05C,'DFLT':0x00000023,'RW':'RW','FIELDS':{ # 0x5003
'reg_ddrc_wr_odt_hold': {'r':(12,15),'d':0,'c':'(Cycles to hold ODT for write command-1). For burst4 - 2, for burst8 - 4'}, # 0x5
'reg_ddrc_rd_odt_hold': {'r':( 8,11),'d':0,'c':'unused'},
......@@ -486,59 +486,68 @@ DDRC_DEFS={ #not all fields are defined currently
# Slice1: fifo_we_ratio_slice_1[10:0] = {Reg_6B[10:9],Reg_6A[18:10]}
# Slice2: fifo_we_ratio_slice_2[10:0] = {Reg_6C[11:9],Reg_6B[18:11]}
# Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,Reg_6C[18:12]}
#seems that Reg_6C is actually Reg_6D, Reg_6B should be Reg_6C, so:
# Slice 0: fifo_we_ratio_slice_0[10:0] = {Reg_6A[9],Reg_69[18:9]}
# Slice1: fifo_we_ratio_slice_1[10:0] = {Reg_6C[10:9],Reg_6A[18:10]}
# Slice2: fifo_we_ratio_slice_2[10:0] = {Reg_6D[11:9],Reg_6C[18:11]}
# Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,Reg_6D[18:12]}
'reg_69': {'OFFS': 0x1A4,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 0','FIELDS':{
'phy_reg_status_fifo_w e_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
'reg_6a': {'OFFS': 0x1A8,'DFLT':0x000F0000,'RW':'R','FIELDS':{
'phy_reg_status_fifo_w e_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
'reg_6b': {'OFFS': 0x1AC,'DFLT':0x000F0000,'RW':'R','FIELDS':{ #may be different bits/default values
'phy_reg_status_fifo_w e_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
'phy_reg_status_fifo_we_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
'reg_6a': {'OFFS': 0x1A8,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 1','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
# 'reg_6b': {'OFFS': 0x1AC,'DFLT':0x000F0000,'RW':'R','FIELDS':{ #may be different bits/default values
# 'phy_reg_status_fifo_we_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
# 'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
# 'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
# u32 reserved8[1]; /* 0x1AC */
'reg_6c': {'OFFS': 0x1B0,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 2','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'phy_reg_bist_err': {'r':( 0, 8),'d':0, 'm':'R','c':'Mismatch error from BIST checker, 1 bit per data slice'}}},
'reg_6d': {'OFFS': 0x1B4,'DFLT':0x000F0000,'RW':'R','FIELDS':{
'reg_6d': {'OFFS': 0x1B4,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 3','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'phy_reg_bist_err': {'r':( 0, 8),'d':0, 'm':'R','c':'Mismatch error from BIST checker, 1 bit per data slice'}}},
'reg_6e': {'OFFS': 0x1B8,'RW':'R','COMMENTS':'Training results for data slice 0','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_rdlvl_fifowein_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_bist_err': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'phy_reg_rdlvl_dqs_ratio': {'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_wrlvl_dq_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_wrlvl_dqs_ratio': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'reg_6f': {'OFFS': 0x1BC,'RW':'R','COMMENTS':'Training results for data slice 1','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_rdlvl_fifowein_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_bist_err': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'phy_reg_rdlvl_dqs_ratio': {'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_wrlvl_dq_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_wrlvl_dqs_ratio': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'reg_70': {'OFFS': 0x1C0,'RW':'R','COMMENTS':'Training results for data slice 2','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_rdlvl_fifowein_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_bist_err': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'phy_reg_rdlvl_dqs_ratio': {'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_wrlvl_dq_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_wrlvl_dqs_ratio': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'reg_71': {'OFFS': 0x1C4,'RW':'R','COMMENTS':'Training results for data slice 3','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_rdlvl_fifowein_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_bist_err': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'phy_reg_rdlvl_dqs_ratio': {'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_wrlvl_dq_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_wrlvl_dqs_ratio': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
# u32 reserved9[1]; /* 0x1C8 */
'phy_dll_sts0': {'OFFS': 0x1CC,'DFLT':0x00000000,'RW':'R','COMMENTS':'Slave DLL results for data slice 0','FIELDS':{
'phy_reg_status_wr_dqs_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Delay for write DQS slave DLL'},
'phy_reg_status_wr_dat a_slave_dll_value':{'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_wr_data_slave_dll_value': {'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_rd_dqs_slave_dll_value': {'r':( 0, 8),'d':0, 'm':'R','c':'Delay for read data slave DLL'}}},
'phy_dll_sts1': {'OFFS': 0x1D0,'DFLT':0x00000000,'RW':'R','COMMENTS':'Slave DLL results for data slice 1','FIELDS':{
'phy_reg_status_wr_dqs_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Delay for write DQS slave DLL'},
'phy_reg_status_wr_dat a_slave_dll_value':{'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_wr_data_slave_dll_value': {'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_rd_dqs_slave_dll_value': {'r':( 0, 8),'d':0, 'm':'R','c':'Delay for read data slave DLL'}}},
'phy_dll_sts2': {'OFFS': 0x1D4,'DFLT':0x00000000,'RW':'R','COMMENTS':'Slave DLL results for data slice 2','FIELDS':{
'phy_reg_status_wr_dqs_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Delay for write DQS slave DLL'},
'phy_reg_status_wr_dat a_slave_dll_value':{'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_wr_data_slave_dll_value': {'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_rd_dqs_slave_dll_value': {'r':( 0, 8),'d':0, 'm':'R','c':'Delay for read data slave DLL'}}},
'phy_dll_sts3': {'OFFS': 0x1D8,'DFLT':0x00000000,'RW':'R','COMMENTS':'Slave DLL results for data slice 3','FIELDS':{
'phy_reg_status_wr_dqs_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Delay for write DQS slave DLL'},
'phy_reg_status_wr_dat a_slave_dll_value':{'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_wr_data_slave_dll_value': {'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_rd_dqs_slave_dll_value': {'r':( 0, 8),'d':0, 'm':'R','c':'Delay for read data slave DLL'}}},
# u32 reserved10[1]; /* 0x1DC */
'dll_lock_sts': {'OFFS': 0x1E0,'DFLT':0x00000000,'RW':'R','COMMENTS':'DLL lock status','FIELDS':{
......@@ -553,6 +562,7 @@ DDRC_DEFS={ #not all fields are defined currently
'phy_reg_status_phy_ctrl_dll_lock': {'r':(19,19),'d':0, 'm':'R','c':'PHY control Master DLL locked'},
'phy_reg_status_of_out_delay_value': {'r':(10,18), 'm':'R','c':'Master DLL output filter output: 10:11 - fine, 12:18 - coarse'},
'phy_reg_status_of_in_delay_value': {'r':( 0, 9), 'm':'R','c':'Master DLL output filter input: 10:11 - fine, 12:18 - coarse'}}},
'phy_ctrl_sts_reg2': {'OFFS': 0x1E8,'DFLT':0x00000000,'RW':'R','COMMENTS':'PHY control status 2','FIELDS':{
'phy_reg_status_phy_ctrl_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Read DQS slave DLL input'},
'reserved': {'r':( 9,17),'d':0, 'm':'R','c':'reserved'},
......
ezynq_ddrcfg_defs.py
View file @ 435a11b3
......@@ -79,7 +79,69 @@ DDR_CFG_DEFS=[
'DESCRIPTION':'Drive strength negative for driving DDR DQ/DQS signals'},
{'NAME':'BIDIR_DRIVE_POS', 'CONF_NAME':'CONFIG_EZYNQ_DDR_BIDIR_DRIVE_POS','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':28,
'DESCRIPTION':'Slew rate positive for driving DDR DQ/DQS signals'},
###### Board Dependent (to be calculated) ######
{'NAME':'PHY_WRLV_INIT_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for write leveling FSM, slice 0'},
{'NAME':'PHY_WRLV_INIT_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for write leveling FSM, slice 1'},
{'NAME':'PHY_WRLV_INIT_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for write leveling FSM, slice 2'},
{'NAME':'PHY_WRLV_INIT_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for write leveling FSM, slice 3'},
{'NAME':'PHY_GTLV_INIT_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for gate leveling FSM, slice 0'},
{'NAME':'PHY_GTLV_INIT_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for gate leveling FSM, slice 1'},
{'NAME':'PHY_GTLV_INIT_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for gate leveling FSM, slice 2'},
{'NAME':'PHY_GTLV_INIT_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for gate leveling FSM, slice 3'},
{'NAME':'PHY_RD_DQS_SLAVE_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for read DQS slave DLL (256 - clock period), slice 0'},
{'NAME':'PHY_RD_DQS_SLAVE_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for read DQS slave DLL (256 - clock period), slice 1'},
{'NAME':'PHY_RD_DQS_SLAVE_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for read DQS slave DLL (256 - clock period), slice 2'},
{'NAME':'PHY_RD_DQS_SLAVE_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for read DQS slave DLL (256 - clock period), slice 3'},
{'NAME':'PHY_WR_DQS_SLAVE_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Ratio for write DQS slave DLL (256 - clock period), slice 0'},
{'NAME':'PHY_WR_DQS_SLAVE_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Ratio for write DQS slave DLL (256 - clock period), slice 1'},
{'NAME':'PHY_WR_DQS_SLAVE_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Ratio for write DQS slave DLL (256 - clock period), slice 2'},
{'NAME':'PHY_WR_DQS_SLAVE_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Ratio for write DQS slave DLL (256 - clock period), slice 3'},
{'NAME':'PHY_FIFO_WE_SLAVE_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for FIFO WE slave DLL (256 - clock period), slice 0'},
{'NAME':'PHY_FIFO_WE_SLAVE_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for FIFO WE slave DLL (256 - clock period), slice 1'},
{'NAME':'PHY_FIFO_WE_SLAVE_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for FIFO WE slave DLL (256 - clock period), slice 2'},
{'NAME':'PHY_FIFO_WE_SLAVE_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for FIFO WE slave DLL (256 - clock period), slice 3'},
{'NAME':'PHY_WR_DATA_SLAVE_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x40,
'DESCRIPTION':'Ratio for write data slave DLL (256 - clock period), slice 0'},
{'NAME':'PHY_WR_DATA_SLAVE_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x40,
'DESCRIPTION':'Ratio for write data slave DLL (256 - clock period), slice 1'},
{'NAME':'PHY_WR_DATA_SLAVE_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x40,
'DESCRIPTION':'Ratio for write data slave DLL (256 - clock period), slice 2'},
{'NAME':'PHY_WR_DATA_SLAVE_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x40,
'DESCRIPTION':'Ratio for write data slave DLL (256 - clock period), slice 3'},
{'NAME':'PHY_CTRL_SLAVE_RATIO', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x80,
'DESCRIPTION':'Ratio for address/command (256 - clock period)'},
{'NAME':'PHY_INVERT_CLK', 'CONF_NAME':'CONFIG_EZYNQ_PHY_INVERT_CLK','TYPE':'B','MANDATORY':True,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Invert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS)'},
{'NAME':'SILICON', 'CONF_NAME':'CONFIG_EZYNQ_SILICON','TYPE':'T','MANDATORY':True,'DERIVED':False,'DEFAULT':'3',
'DESCRIPTION':'Zynq silicon revision'},
###### DDR Datasheet #######
{'NAME':'PARTNO', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_PARTNO','TYPE':'T','MANDATORY':True,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Memory part number (currently not used - derive some parameters later)'},
......@@ -137,8 +199,8 @@ DDR_CFG_DEFS=[
'DESCRIPTION':'MODE REGISTER SET update delay (in tCK)'},
{'NAME':'T_MOD', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_T_MOD','TYPE':'F','MANDATORY':False,'DERIVED':False,'DEFAULT':15.0,
'DESCRIPTION':'MODE REGISTER SET update delay (ns).'},
{'NAME':'T_WLMRD', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_T_WLMRD','TYPE':'F','MANDATORY':False,'DERIVED':False,'DEFAULT':40.0,
'DESCRIPTION':'Write leveling : time to the first DQS rising edge (ns).'},
{'NAME':'WLMRD', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_WLMRD','TYPE':'I','MANDATORY':False,'DERIVED':False,'DEFAULT':40,
'DESCRIPTION':'Write leveling : time to the first DQS rising edge (cycles).'},
{'NAME':'CKE', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_CKE','TYPE':'I','MANDATORY':False,'DERIVED':False,'DEFAULT':3,
'DESCRIPTION':'CKE min pulse width (in tCK)'},
{'NAME':'T_CKE', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_T_CKE','TYPE':'F','MANDATORY':False,'DERIVED':False,'DEFAULT':7.5,
......@@ -182,7 +244,7 @@ DDR_CFG_DEFS=[
# CONFIG_EZYNQ_DDR_DS_RRD = 4
# CONFIG_EZYNQ_DDR_DS_T_RRD = 10.0
# CONFIG_EZYNQ_DDR_DS_MRD = 4
# CONFIG_EZYNQ_DDR_DS_T_WLMRD = 40.0 #
# CONFIG_EZYNQ_DDR_DS_WLMRD = 40 #
# CONFIG_EZYNQ_DDR_DS_T_MOD = 15.0
# CONFIG_EZYNQ_DDR_DS_MOD = 12
......
ezynq_ddriob_def.py
View file @ 435a11b3
......@@ -181,7 +181,7 @@ DDRIOB_DEFS={ #not all fields are defined currently
'nref_opt4': {'r':(11,13),'d':0, 'c':'DCI Calibration mode - use values in the Calibration Table'}, #1
'nref_opt2': {'r':( 8,10),'d':0, 'c':'DCI Calibration mode - use values in the Calibration Table'},
'nref_opt1': {'r':( 6, 7),'d':0, 'c':'DCI Calibration mode - use values in the Calibration Table'},
'vrn_out': {'r':( 5, 5),'d':1, 'c':'Reserved'}, #1
'vrn_out': {'r':( 5, 5),'d':1, 'c':'1 for silicon 1,2; unused (0) for silicon 3'}, #1
'vrp_out': {'r':( 4, 4),'d':0, 'c':'Reserved'},
'vrn_tri': {'r':( 3, 3),'d':0, 'c':'Reserved'},
'vrp_tri': {'r':( 2, 2),'d':0, 'c':'Reserved'},
......
ezynq_feature_config.py
View file @ 435a11b3
......@@ -121,10 +121,13 @@ class EzynqFeatures:
else:
raise Exception(self.ERRORS['ERR_NOT_AN_INTEGER']+': '+line['VALUE'] +' is not a valid INTEGER value for parameter '+ conf_name)
elif (feature['TYPE']=='F'):
try:
value= float(value)
except:
raise Exception(self.ERRORS['ERR_NOT_A_FLOAT']+': '+line['VALUE'] +' is not a valid FLOAT value for parameter '+ conf_name)
if value == 'Y':
value=1.0
else:
try:
value= float(value)
except:
raise Exception(self.ERRORS['ERR_NOT_A_FLOAT']+': '+line['VALUE'] +' is not a valid FLOAT value for parameter '+ conf_name)
elif (feature['TYPE']=='B'):
if value in self.BOOLEANS[1]:
value=True
......@@ -136,6 +139,8 @@ class EzynqFeatures:
raise Exception(self.ERRORS['ERR_NOT_A_BOOLEAN']+': '+line['VALUE'] +' is not a valid boolean value for parameter '+ conf_name+
'. Valid for "True" are:'+str(self.BOOLEANS[1])+', for "False" - '+str(self.BOOLEANS[0]))
elif (feature['TYPE']=='T'):
if value == 'Y':
value='1'
pass #keep string value
self.pars[name]=value
self.defined.add(name)
......@@ -313,8 +318,12 @@ class EzynqFeatures:
# print value
if row_class=="odd": row_class="even"
else: row_class="odd"
if (feature['TYPE']=='H') and isinstance(feature['DEFAULT'],int) and (feature['DEFAULT']>9):
sDefault=hex(feature['DEFAULT'])
else:
sDefault=str(feature['DEFAULT'])
html_file.write('<tr class="'+row_class+'"><td><b>'+feature['CONF_NAME']+'</b></td><td>'+str(value)+'</td><td>'+par_type+