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ezynq
Commit 435a11b3 authored by Andrey Filippov's avatar Andrey Filippov
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Adding support for elphel393, new configurations, bug fixes

parent b2b3c812
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Showing with 1204 additions and 114 deletions
ezynq_ddr.py
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......@@ -45,6 +45,7 @@ class EzynqDDR:
self.features=ezynq_feature_config.EzynqFeatures(self.DDR_CFG_DEFS,0) #DDR_CFG_DEFS
self.ddrc_register_set= ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits)
self.ddriob_register_set=ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits)
def generate_command_queue_empty(self):
# generate code to be included in u-boot for testing DDR command queue
......@@ -58,6 +59,17 @@ class EzynqDDR:
self.features.parse_features(raw_configs)
def check_missing_features(self):
self.features.check_missing_features()
if (self.features.get_par_value('SILICON')=='1'):
self.silicon=1
elif (self.features.get_par_value('SILICON')=='2'):
self.silicon=2
elif (self.features.get_par_value('SILICON')=='3'):
self.silicon=3
elif (self.features.get_par_value('SILICON')=='3.1'):
self.silicon=3
else:
self.silicon=3
def html_list_features(self,html_file):
if not html_file:
return
......@@ -402,6 +414,7 @@ class EzynqDDR:
('reg_ddrc_pad_pd', padPD), # 0x0
('reg_ddrc_t_xp', XP), # 0x4
('reg_ddrc_wr2rd', WR2RD), # 0xe
# ('reg_ddrc_wr2rd', WR2RD | 0x10), # TODO: REMOVE !!!!
('reg_ddrc_rd2wr', RD2WR), # 0x7
('reg_ddrc_write_latency', write_latency)),force,warn) #5
# reg DRAM_param_reg3, 0x270872d0 , 0x272872d0, 0x272872d0 (first time reg_ddrc_sdram is not set, the rest is the same)
......@@ -420,7 +433,7 @@ class EzynqDDR:
('reg_ddrc_read_latency', RL), #7
('reg_ddrc_en_dfi_dram_clk_disable',en_dfi_dram_clk_disable), #0
('reg_ddrc_mobile', (0,1)[is_LPDDR2]), # 0
('reg_ddrc_sdram', 1), # Shown reserved/default==0, but actually is set to 1 (2 and 3-rd time)
('reg_ddrc_sdram', (1,0)[self.silicon==3] ), # Shown reserved/default==0, but actually is set to 1 (2 and 3-rd time)
('reg_ddrc_refresh_to_x32', ddrc_refresh_to_x32), # 8
('reg_ddrc_t_rp', RP), # 7
('reg_ddrc_refresh_margin', refresh_margin), # 2
......@@ -429,8 +442,9 @@ class EzynqDDR:
# reg DRAM_param_reg4, 0, 0x3c, 0x3c
ddrc_register_set.set_word ('dram_param_reg4',0x0,force) # reset all fields. This register is controlled by the hardware during automatic initialization
#Maybe just the LSBB (reg_ddrc_en_2t_timing_mode) is needed for "2t timing mode" - is it non-common?
ddrc_register_set.set_bitfields('dram_param_reg4',(('reg_ddrc_max_rank_rd', 0xf)),force,warn) # Not documented, but appears to be set in 2-nd and 3-rd round
ddrc_register_set.set_bitfields('dram_param_reg4',(('reg_ddrc_max_rank_rd', (0xf,0)[self.silicon==3])),force,warn) # Not documented, but appears to be set in 2-nd and 3-rd round
# reg DRAM_init_param, 0x2007 always (default)
MRD = self.features.get_par_value('CCD')
......@@ -439,6 +453,8 @@ class EzynqDDR:
ddrc_register_set.set_bitfields('dram_init_param',(('reg_ddrc_t_mrd', MRD), # 0x4
('reg_ddrc_pre_ocd_x32', pre_ocd_x32), # 0x0
('reg_ddrc_final_wait_x32', final_wait_x32)),force,warn) # 0x7
# reg DRAM_emr_reg, 0x8 always (default)
# ddrc_register_set.set_word ('dram_emr_reg', 0x8, force)
emr3=0 # Only 3 LSBs are used by DDR and should be set to 0 - correct values will be set by the DDRC
......@@ -612,7 +628,11 @@ class EzynqDDR:
#
if is_DDR3:
t_post_cke=400.0
t_pre_cke= 200000.0
# t_pre_cke= 200000.0
t_pre_cke= 500000.0 # as generated by Vivado 2013.3, maybe same applies to other DDRx
#TODO: REMOVE !!!!
# t_pre_cke= 200000.0 # as generated by Vivado 2013.3, maybe same applies to other DDRx
elif is_DDR2:
t_post_cke=400.0
t_pre_cke= 200000.0
......@@ -684,9 +704,9 @@ class EzynqDDR:
# reg DRAM_odt_reg, 0x3c000, 0x3c248,0x3c248
# Could not find documentation, default value may work (first time 3 default/do not change values were different
rank0_wr_odt = 1 # default, was 0 first time
rank1_rd_odt = 1 # default, was 0 first time
rank1_wr_odt = 1 # default, was 0 first time
rank0_wr_odt = (1,0)[self.silicon==3] # default, was 0 first time
rank1_rd_odt = (1,0)[self.silicon==3] # default, was 0 first time
rank1_wr_odt = (1,0)[self.silicon==3] # default, was 0 first time
wr_local_odt = 3 # default
idle_local_odt= 3 # default
......@@ -726,8 +746,8 @@ class EzynqDDR:
),force,warn)
# reg DLL_calib, 0x0, then 2 times 0x101 (default). Does it need to be 0 before training. Not listed in 10-11 - probably can be skipped during init
dis_dll_calib = 0 # if 1 - disable automatic periodic DLL correction
dll_calib_to_max_x1024 = 1 # reserved, do not modify
dll_calib_to_min_x1024 = 1 # reserved, do not modify
dll_calib_to_max_x1024 = (1,0)[self.silicon==3] # reserved, do not modify
dll_calib_to_min_x1024 = (1,0)[self.silicon==3] # reserved, do not modify
ddrc_register_set.set_bitfields('dll_calib',(('reg_ddrc_dis_dll_calib', dis_dll_calib), # 0
('reg_ddrc_dll_calib_to_max_x1024', dll_calib_to_max_x1024), # 1
('reg_ddrc_dll_calib_to_min_x1024', dll_calib_to_min_x1024) # 1
......@@ -772,7 +792,7 @@ class EzynqDDR:
),force,warn)
# reg ctrl_reg3 0x284141 - all 3 times (non-default, default=0x00284027)
if is_DDR3: # other - N/A
dfi_t_wlmrd= int(math.ceil(self.features.get_par_value('T_WLMRD')/tCK))
dfi_t_wlmrd= self.features.get_par_value('WLMRD')
rdlvl_rr = 0x41 # default = 0x40 (Did not understand how to calculate, using actual for DDR3)
ddrc_register_set.set_bitfields('ctrl_reg3',(('reg_ddrc_dfi_t_wlmrd', dfi_t_wlmrd),
('reg_ddrc_rdlvl_rr', rdlvl_rr)),force,warn) # 0x28 DDR3 only: tWLMRD from DRAM specs
......@@ -863,12 +883,17 @@ class EzynqDDR:
),force,warn)
# reg reg_2c dflt=0 act=0xffffff
# use_rd_data_eye_level = (0,1)[self.features.get_par_value('TRAIN_DATA_EYE')]
# use_rd_dqs_gate_level = (0,1)[self.features.get_par_value('TRAIN_READ_GATE')]
# use_wr_level = (0,1)[self.features.get_par_value('TRAIN_WRITE_LEVEL')]
dfi_rdlvl_max_x1024=0xfff # using actual/recommended
dfi_wrlvl_max_x1024=0xfff # using actual/recommended
#Vivado 2013.3 set DFI training to 1
ddrc_register_set.set_bitfields('reg_2c',(
('reg_ddrc_dfi_rd_data_eye_train', 0), # 0 DDR3 and LPDDR2 only: 1 - read data eye training (part of init sequence)
('reg_ddrc_dfi_rd_dqs_gate_level', 0), # 0 1 - Read DQS gate leveling mode (DDR3 DFI only)
('reg_ddrc_dfi_wr_level_en', 0), # 0 1 - Write leveling mode (DDR3 DFI only)
('reg_ddrc_dfi_rd_data_eye_train', use_rd_data_eye_level), # 0 DDR3 and LPDDR2 only: 1 - read data eye training (part of init sequence)
('reg_ddrc_dfi_rd_dqs_gate_level', use_rd_dqs_gate_level), # 0 1 - Read DQS gate leveling mode (DDR3 DFI only)
('reg_ddrc_dfi_wr_level_en', use_wr_level), # 0 1 - Write leveling mode (DDR3 DFI only)
('ddrc_reg_trdlvl_max_error', 0), # 0 READONLY: DDR3 and LPDDR2 only: leveling/gate training timeout (clear on write)
('ddrc_reg_twrlvl_max_error', 0), # 0 READONLY: DDR3 only: write leveling timeout (clear on write)
('dfi_rdlvl_max_x1024',dfi_rdlvl_max_x1024), # 0xfff Read leveling maximal time in 1024 clk. Typical value 0xFFF
......@@ -898,6 +923,11 @@ class EzynqDDR:
programECC = True
if programECC:
# reg che_ecc_control_reg_offset (offs=0xc4) : 0 - always, ==dflt
ddrc_register_set.set_bitfields('che_ecc_control_reg_offset',(
('clear_correctable_dram_ecc_error', 1), # 0 1 - clear correctable log (valid+counters)
('clear_uncorrectable_dram_ecc_error', 1), # 0 1 - clear uncorrectable log (valid+counters)
),force,warn)
ddrc_register_set.flush()
ddrc_register_set.set_bitfields('che_ecc_control_reg_offset',(
('clear_correctable_dram_ecc_error', 0), # 0 1 - clear correctable log (valid+counters)
('clear_uncorrectable_dram_ecc_error', 0), # 0 1 - clear uncorrectable log (valid+counters)
......@@ -1031,82 +1061,102 @@ class EzynqDDR:
('reg_phy_rdlvl_inc_mode', 0), #
('reg_phy_data_slice_in_use',slice_in_use3), # 1 Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 3 is valid (always 1)
),force,warn)
gatelvl_init_ratio0=self.features.get_par_value('PHY_GTLV_INIT_RATIO_0')
gatelvl_init_ratio1=self.features.get_par_value('PHY_GTLV_INIT_RATIO_1')
gatelvl_init_ratio2=self.features.get_par_value('PHY_GTLV_INIT_RATIO_2')
gatelvl_init_ratio3=self.features.get_par_value('PHY_GTLV_INIT_RATIO_3')
wrlvl_init_ratio0=self.features.get_par_value('PHY_WRLV_INIT_RATIO_0')
wrlvl_init_ratio1=self.features.get_par_value('PHY_WRLV_INIT_RATIO_1')
wrlvl_init_ratio2=self.features.get_par_value('PHY_WRLV_INIT_RATIO_2')
wrlvl_init_ratio3=self.features.get_par_value('PHY_WRLV_INIT_RATIO_3')
# reg phy_init_ratio0, offs=0x12C dflt:0x0 actual: 0x0
ddrc_register_set.set_bitfields('phy_init_ratio0',( # PHY init ratio register for data slice 0
('reg_phy_gatelvl_init_ratio', 0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 0
('reg_phy_wrlvl_init_ratio', 0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 0
('reg_phy_gatelvl_init_ratio', gatelvl_init_ratio0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 0
('reg_phy_wrlvl_init_ratio', wrlvl_init_ratio0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 0
),force,warn)
# reg phy_init_ratio1, offs=0x130 dflt:0x0 actual: 0x0
ddrc_register_set.set_bitfields('phy_init_ratio1',( # PHY init ratio register for data slice 1
('reg_phy_gatelvl_init_ratio', 0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 1
('reg_phy_wrlvl_init_ratio', 0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 1
('reg_phy_gatelvl_init_ratio', gatelvl_init_ratio1), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 1
('reg_phy_wrlvl_init_ratio', wrlvl_init_ratio1), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 1
),force,warn)
# reg phy_init_ratio2, offs=0x134 dflt:0x0 actual: 0x0
ddrc_register_set.set_bitfields('phy_init_ratio2',( # PHY init ratio register for data slice 2
('reg_phy_gatelvl_init_ratio', 0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 2
('reg_phy_wrlvl_init_ratio', 0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 2
('reg_phy_gatelvl_init_ratio', gatelvl_init_ratio2), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 2
('reg_phy_wrlvl_init_ratio', wrlvl_init_ratio2), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 2
),force,warn)
# reg phy_init_ratio3, offs=0x138 dflt:0x0 actual: 0x0
ddrc_register_set.set_bitfields('phy_init_ratio3',( # PHY init ratio register for data slice 3
('reg_phy_gatelvl_init_ratio', 0), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 3
('reg_phy_wrlvl_init_ratio', 0), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 3
('reg_phy_gatelvl_init_ratio', gatelvl_init_ratio3), # 0 User-programmable init ratio used by Gate Leveling FSM, data slice 3
('reg_phy_wrlvl_init_ratio', wrlvl_init_ratio3), # 0 User-programmable init ratio used by Write Leveling FSM, data slice 3
),force,warn)
dqs_slave_ratio0=0x35 # default=40
dqs_slave_ratio1=0x35 # default=40
dqs_slave_ratio2=0x35 # default=40
dqs_slave_ratio3=0x35 # default=40
rd_dqs_slave_ratio0=0x35 # default=40
rd_dqs_slave_ratio1=0x35 # default=40
rd_dqs_slave_ratio2=0x35 # default=40
rd_dqs_slave_ratio3=0x35 # default=40
# reg phy_rd_dqs_cfg0, offs=0x140 dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg0',( # PHY read DQS configuration register for data slice 0
('reg_phy_rd_dqs_slave_delay', 0), # 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 0
('reg_phy_rd_dqs_slave_force', 0), # 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 0
('reg_phy_rd_dqs_slave_ratio', dqs_slave_ratio0), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 0
('reg_phy_rd_dqs_slave_ratio', rd_dqs_slave_ratio0), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 0
),force,warn)
# reg phy_rd_dqs_cfg1, offs=0x144 dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg1',( # PHY read DQS configuration register for data slice 1
('reg_phy_rd_dqs_slave_delay', 0), # 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 1
('reg_phy_rd_dqs_slave_force', 0), # 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 1
('reg_phy_rd_dqs_slave_ratio', dqs_slave_ratio1), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 1
('reg_phy_rd_dqs_slave_ratio', rd_dqs_slave_ratio1), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 1
),force,warn)
# reg phy_rd_dqs_cfg2, offs=0x148 dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg2',( # PHY read DQS configuration register for data slice 2
('reg_phy_rd_dqs_slave_delay', 0), # 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 2
('reg_phy_rd_dqs_slave_force', 0), # 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 2
('reg_phy_rd_dqs_slave_ratio', dqs_slave_ratio2), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 2
('reg_phy_rd_dqs_slave_ratio', rd_dqs_slave_ratio2), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 2
),force,warn)
# reg phy_rd_dqs_cfg3, offs=0x14c dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg3',( # PHY read DQS configuration register for data slice 3
('reg_phy_rd_dqs_slave_delay', 0), # 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 3
('reg_phy_rd_dqs_slave_force', 0), # 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 3
('reg_phy_rd_dqs_slave_ratio', dqs_slave_ratio3), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 3
('reg_phy_rd_dqs_slave_ratio', rd_dqs_slave_ratio3), # 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 3
),force,warn)
wr_dqs_slave_ratio0=self.features.get_par_value('PHY_WR_DQS_SLAVE_RATIO_0')
wr_dqs_slave_ratio1=self.features.get_par_value('PHY_WR_DQS_SLAVE_RATIO_1')
wr_dqs_slave_ratio2=self.features.get_par_value('PHY_WR_DQS_SLAVE_RATIO_2')
wr_dqs_slave_ratio3=self.features.get_par_value('PHY_WR_DQS_SLAVE_RATIO_3')
# reg phy_wr_dqs_cfg0, offs=0x154 dflt:0 actual: 0
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg0',( # ,PHY write DQS configuration register for data slice 0
('reg_phy_wr_dqs_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 0
('reg_phy_wr_dqs_slave_force', 0), # 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 0
('reg_phy_wr_dqs_slave_ratio', 0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 0. Program manual training ratio
('reg_phy_wr_dqs_slave_ratio', wr_dqs_slave_ratio0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 0. Program manual training ratio
),force,warn)
# reg phy_wr_dqs_cfg0, offs=0x158 dflt:0 actual: 0
# reg phy_wr_dqs_cfg1, offs=0x158 dflt:0 actual: 0
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg1',( # ,PHY write DQS configuration register for data slice 1
('reg_phy_wr_dqs_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 1
('reg_phy_wr_dqs_slave_force', 0), # 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 1
('reg_phy_wr_dqs_slave_ratio', 0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 1. Program manual training ratio
('reg_phy_wr_dqs_slave_ratio', wr_dqs_slave_ratio1), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 1. Program manual training ratio
),force,warn)
# reg phy_wr_dqs_cfg0, offs=0x15c dflt:0 actual: 0
# reg phy_wr_dqs_cfg2, offs=0x15c dflt:0 actual: 0
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg2',( # ,PHY write DQS configuration register for data slice 2
('reg_phy_wr_dqs_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 2
('reg_phy_wr_dqs_slave_force', 0), # 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 2
('reg_phy_wr_dqs_slave_ratio', 0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 2. Program manual training ratio
('reg_phy_wr_dqs_slave_ratio', wr_dqs_slave_ratio2), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 2. Program manual training ratio
),force,warn)
# reg phy_wr_dqs_cfg0, offs=0x160 dflt:0 actual: 0
# reg phy_wr_dqs_cfg3, offs=0x160 dflt:0 actual: 0
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg3',( # ,PHY write DQS configuration register for data slice 3
('reg_phy_wr_dqs_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 3
('reg_phy_wr_dqs_slave_force', 0), # 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 3
('reg_phy_wr_dqs_slave_ratio', 0), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 3. Program manual training ratio
('reg_phy_wr_dqs_slave_ratio', wr_dqs_slave_ratio3), # 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 3. Program manual training ratio
),force,warn)
fifo_we_slave_ratio0=0x35 # default=40
fifo_we_slave_ratio1=0x35 # default=40
fifo_we_slave_ratio2=0x35 # default=40
fifo_we_slave_ratio3=0x35 # default=40
fifo_we_slave_ratio0=self.features.get_par_value('PHY_FIFO_WE_SLAVE_RATIO_0')
fifo_we_slave_ratio1=self.features.get_par_value('PHY_FIFO_WE_SLAVE_RATIO_1')
fifo_we_slave_ratio2=self.features.get_par_value('PHY_FIFO_WE_SLAVE_RATIO_2')
fifo_we_slave_ratio3=self.features.get_par_value('PHY_FIFO_WE_SLAVE_RATIO_3')
# reg phy_we_cfg0, offs=0x168 dflt:0x40 actual: 0x35
ddrc_register_set.set_bitfields('phy_we_cfg0',( # PHY FIFO write enable configuration register for data slice 0
......@@ -1132,10 +1182,10 @@ class EzynqDDR:
('reg_phy_fifo_we_in_force', 0), # 0 0 - use reg_phy_fifo_we_slave_ratio for fifo_we_0 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 3
('reg_phy_fifo_we_slave_ratio',fifo_we_slave_ratio3), # 0x35 Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 3. Program manual training ratio
),force,warn)
wr_data_slave_ratio0=0x40
wr_data_slave_ratio1=0x40
wr_data_slave_ratio2=0x40
wr_data_slave_ratio3=0x40
wr_data_slave_ratio0=self.features.get_par_value('PHY_WR_DATA_SLAVE_RATIO_0')
wr_data_slave_ratio1=self.features.get_par_value('PHY_WR_DATA_SLAVE_RATIO_1')
wr_data_slave_ratio2=self.features.get_par_value('PHY_WR_DATA_SLAVE_RATIO_2')
wr_data_slave_ratio3=self.features.get_par_value('PHY_WR_DATA_SLAVE_RATIO_3')
# reg wr_data_slv0, offs=0x17c dflt:0x80 actual: 0x40
ddrc_register_set.set_bitfields('wr_data_slv0',( # PHY write data slave ratio configuration register for data slice 0
('reg_phy_wr_data_slave_delay', 0), # 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 0
......@@ -1161,10 +1211,16 @@ class EzynqDDR:
('reg_phy_wr_data_slave_ratio',wr_data_slave_ratio3), # 0x40 Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 3. Program manual training ratio
),force,warn)
# reg reg_64, offs=0x190 dflt:0x10020000 actual:0x20000(first time)-0x10020000-0x10020000
use_rank0_delays = 1 # marked as reserved, but actually is first set to 0 - maybe not needed
use_rank0_delays = (1,0)[self.silicon==3] # marked as reserved, but actually is first set to 0 - maybe not needed
phy_lpddr= (0,1)[is_LPDDR2]
ctrl_slave_ratio=0x80 # defualt/actual
phy_ctrl_slave_ratio=self.features.get_par_value('PHY_CTRL_SLAVE_RATIO') # 0x80 # default/actual
sel_logic = 0 # Read leveling algorithm select - 0:algorithm 1, 1: algorithm 2
phy_invert_clkout=self.features.get_par_value('PHY_INVERT_CLK')
#define CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO 0x100 /* Ratio for address/command (256 - clock period) */
#define CONFIG_EZYNQ_PHY_INVERT_CLK /* RInvert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
ddrc_register_set.set_bitfields('reg_64',( # Training control 2
('reg_phy_int_lpbk', 0), # reserved
('reg_phy_cmd_latency', 0), # 1: Delay command to PHY by a FF
......@@ -1172,10 +1228,10 @@ class EzynqDDR:
('reg_phy_use_rank0_delays', use_rank0_delays), # reserved
('reg_phy_ctrl_slave_delay', 0), # when reg_phy_rd_dqs_slave_force==1 this value (combined with bits 18:19 of reg_65) set address/command slave DLL
('reg_phy_ctrl_slave_force', 0), # 0:use reg_phy_ctrl_slave_ratio for addr/cmd slave DLL, 1 - overwrite with reg_phy_ctrl_slave_delay
('reg_phy_ctrl_slave_ratio',ctrl_slave_ratio), # address/command delay in clock/256
('reg_phy_ctrl_slave_ratio',phy_ctrl_slave_ratio), # address/command delay in clock/256
('reg_phy_sel_logic', sel_logic), # Read leveling algorithm select - 0:algorithm 1, 1: algorithm 2
('reg_phy_all_dq_mpr_rd_resp',0), # reserved
('reg_phy_invert_clkout', 0), # 1 - invert clock polarity to DRAM
('reg_phy_invert_clkout', phy_invert_clkout), # 1 - invert clock polarity to DRAM
('reg_phy_bist_mode', 0), # reserved
('reg_phy_bist_force_err', 0), # reserved
('reg_phy_bist_enable', 0), # reserved
......@@ -1215,7 +1271,7 @@ class EzynqDDR:
arb_pri_wr_port3=0x3ff # lowest
# reg axi_priority_wr_port0, offs=0x208 dflt:0x803FF actual: 0x803ff
ddrc_register_set.set_bitfields('axi_priority_wr_port0',( # AXI priority control for write port 0
('reserved1', 0x1), # 0x1
('reserved1', (1,0)[self.silicon==3]), # 0x1
('reg_arb_dis_page_match_wr_portn', 0), # Disable page match feature
('reg_arb_disable_urgent_wr_portn', 0), # Disable urgent for this Write Port
('reg_arb_disable_aging_wr_portn', 0), # Disable aging for this Write Port
......@@ -1226,7 +1282,7 @@ class EzynqDDR:
# reg axi_priority_wr_port1, offs=0x20c dflt:0x803FF actual: 0x803ff
ddrc_register_set.set_bitfields('axi_priority_wr_port1',( # AXI priority control for write port 1
('reserved1', 0x1), # 0x1
('reserved1', 0x1), # 0x1
('reserved1', (1,0)[self.silicon==3]), # 0x1
('reg_arb_dis_page_match_wr_portn', 0), # Disable page match feature
('reg_arb_disable_urgent_wr_portn', 0), # Disable urgent for this Write Port
('reg_arb_disable_aging_wr_portn', 0), # Disable aging for this Write Port
......@@ -1235,7 +1291,7 @@ class EzynqDDR:
),force,warn)
# reg axi_priority_wr_port2, offs=0x210 dflt:0x803FF actual: 0x803ff
ddrc_register_set.set_bitfields('axi_priority_wr_port2',( # AXI priority control for write port 2
('reserved1', 0x1), # 0x1
('reserved1', (1,0)[self.silicon==3]), # 0x1
('reg_arb_dis_page_match_wr_portn', 0), # Disable page match feature
('reg_arb_disable_urgent_wr_portn', 0), # Disable urgent for this Write Port
('reg_arb_disable_aging_wr_portn', 0), # Disable aging for this Write Port
......@@ -1244,7 +1300,7 @@ class EzynqDDR:
),force,warn)
# reg axi_priority_wr_port3, offs=0x214 dflt:0x803FF actual: 0x803ff
ddrc_register_set.set_bitfields('axi_priority_wr_port3',( # AXI priority control for write port 3
('reserved1', 0x1), # 0x1
('reserved1', (1,0)[self.silicon==3]), # 0x1
('reg_arb_dis_page_match_wr_portn', 0), # Disable page match feature
('reg_arb_disable_urgent_wr_portn', 0), # Disable urgent for this Write Port
('reg_arb_disable_aging_wr_portn', 0), # Disable aging for this Write Port
......@@ -1343,11 +1399,14 @@ class EzynqDDR:
ddriob_register_set.flush()# close previous register settings
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),
('enable',1),
('vrn_out',(1,0)[self.silicon==3]),
('nref_opt1',0),
('nref_opt2',0),
('nref_opt4',1),
('pref_opt2',0),
('update_control',0)),force,warn)
ddriob_register_set.flush()# close previous register settings
# add wait for DCI calibration DONE
ddriob_register_set.wait_reg_field_values('ddriob_dci_status',('done',1), True, warn)
......
ezynq_ddrc_defs.py
View file @ 435a11b3
......@@ -72,7 +72,7 @@ DDRC_DEFS={ #not all fields are defined currently
'reg_ddrc_rd2pre': {'r':(23,27),'d': 0x6,'c':'Read to precharge in the same bank'}, #0x4
'reg_ddrc_pad_pd': {'r':(20,22),'d': 0x0,'c':'non-DFI only: pads in/out powersave, in clocks'}, #0x0
'reg_ddrc_t_xp': {'r':(15,19),'d': 0x2,'c':'tXP - power down exit to any operation'}, #0x4
'reg_ddrc_wr2rd': {'r':(10,13),'d': 0x16,'c':'tWTR - write -to -read (clocks)'}, #0xe
'reg_ddrc_wr2rd': {'r':(10,14),'d': 0x16,'c':'tWTR - write -to -read (clocks)'}, #0xe
'reg_ddrc_rd2wr': {'r':( 5, 9),'d': 0x8,'c':'tRTW - read -to -write (clocks)'}, #0x7
'reg_ddrc_write_latency': {'r':( 0, 4),'d': 0x4,'c':'one clock less than actual DDR write latency'}}}, #0x5
'dram_param_reg3': {'OFFS': 0x020,'DFLT':0x250882D0,'RW':'M','FIELDS':{ #272872d0
......@@ -82,7 +82,7 @@ DDRC_DEFS={ #not all fields are defined currently
'reg_ddrc_read_latency': {'r':(24,28),'d': 0x5,'c':'Read Latency, clocks'}, # 0x7
'reg_ddrc_en_dfi_dram_clk_disable': {'r':(23,23),'d': 0,'c':'Enables clock disable...'},
'reg_ddrc_mobile': {'r':(22,22),'d': 0,'c':'0 - DDR2/DDR3, 1 - LPDDR2'},
'reg_ddrc_sdram': {'r':(21,21),'d': 0,'c':'reserved'}, # 0x1
'reg_ddrc_sdram': {'r':(21,21),'d': 0,'c':'silicon 1,2: 1 - SDRAM, 0 - non-SDRAM. Silicon 3: 0'},# 0x1
'reg_ddrc_refresh_to_x32': {'r':(16,20),'d': 0x8,'c':'Dynamic, "speculative refresh"'},
'reg_ddrc_t_rp': {'r':(12,15),'d': 0x8,'c':'tRP'}, # 0x7
'reg_ddrc_refresh_margin': {'r':( 8,11),'d': 0x2,'c':'do refresh this cycles before timer expires'},
......@@ -152,17 +152,17 @@ DDRC_DEFS={ #not all fields are defined currently
'reg_ddrc_addrmap_row_b0': {'r':( 0, 3),'d':0x5,'c':'Selects address bits for row. addr. bit 0, Valid 0..11, int. base=9'}}}, # 0x6
'dram_odt_reg': {'OFFS': 0x048,'DFLT':0x00000249,'RW':'RW','FIELDS':{ # 0x3c248
'reg_ddrc_rank3_wr_odt': {'r':(29,27),'d':0,'c':'reserved'},
'reg_ddrc_rank3_wr_odt': {'r':(29,27),'d':0,'c':'reserved'},
'reg_ddrc_rank3_rd_odt': {'r':(24,26),'d':0,'c':'reserved'},
'reg_ddrc_rank2_wr_odt': {'r':(21,23),'d':0,'c':'reserved'},
'reg_ddrc_rank2_rd_odt': {'r':(18,20),'d':0,'c':'reserved'},
'reg_phy_idle_local_odt': {'r':(16,17),'d':0,'c':'2-bit drive ODT when OE is inactive and no read (power save)'}, # 0x3
'reg_phy_wr_local_odt': {'r':(14,15),'d':0,'c':'ODT strength during write leveling'}, #0x3
'reg_phy_rd_local_odt': {'r':(12,13),'d':0,'c':'ODT strength during read'},
'reg_ddrc_rank1_wr_odt': {'r':( 9,11),'d':0x1,'c':'reserved'},
'reg_ddrc_rank1_rd_odt': {'r':( 6, 8),'d':0x1,'c':'reserved'},
'reg_ddrc_rank0_wr_odt': {'r':( 3, 5),'d':0x1,'c':'reserved'},
'reg_ddrc_rank0_rd_odt': {'r':( 0, 2),'d':0x1,'c':'reserved'}}}, # 0x0
'reg_ddrc_rank1_wr_odt': {'r':( 9,11),'d':0x1,'c':'reserved, unused in silicon 3'},
'reg_ddrc_rank1_rd_odt': {'r':( 6, 8),'d':0x1,'c':'reserved, unused in silicon 3'},
'reg_ddrc_rank0_wr_odt': {'r':( 3, 5),'d':0x1,'c':'reserved, unused in silicon 3'},
'reg_ddrc_rank0_rd_odt': {'r':( 0, 2),'d':0x0,'c':'reserved, unused in silicon 3'}}}, # 0x0
'phy_dbg_reg': {'OFFS': 0x04C,'DFLT':0x00000000,'RW':'R','FIELDS':{
'phy_reg_bc_fifo_re3': {'r':(19,19),'d':0,'m':'R','c':'Debug read capture FIFO read enable for data slice 3'},
'phy_reg_bc_fifo_we3': {'r':(18,18),'d':0,'m':'R','c':'Debug read capture FIFO write enable for data slice 3'},
......@@ -202,8 +202,8 @@ DDRC_DEFS={ #not all fields are defined currently
'ddrc_reg_operating_mode': {'r':( 0, 2),'d':0,'m':'R','c':'DDRC init, 1 - normal, 2 - power down, 3 - self refresh, >=4 - deep power down LPDDR2'}}},
'dll_calib': {'OFFS': 0x058,'DFLT':0x00000101,'RW':'RW','FIELDS':{ # 0x101
'reg_ddrc_dis_dll_calib': {'r':(16,16),'d':0,'c':'Dynamic: 1- disable DLL_calib, 0 - issue DLL_calib periodically'},
'reg_ddrc_dll_calib_to_max_x1024': {'r':( 8,15),'d':0x1,'c':'reserved'},
'reg_ddrc_dll_calib_to_min_x1024': {'r':( 0, 7),'d':0x1,'c':'reserved'}}},
'reg_ddrc_dll_calib_to_max_x1024': {'r':( 8,15),'d':0x1,'c':'reserved, unused in silicon 3'},
'reg_ddrc_dll_calib_to_min_x1024': {'r':( 0, 7),'d':0x1,'c':'reserved, unused in silicon 3'}}},
'odt_delay_hold': {'OFFS': 0x05C,'DFLT':0x00000023,'RW':'RW','FIELDS':{ # 0x5003
'reg_ddrc_wr_odt_hold': {'r':(12,15),'d':0,'c':'(Cycles to hold ODT for write command-1). For burst4 - 2, for burst8 - 4'}, # 0x5
'reg_ddrc_rd_odt_hold': {'r':( 8,11),'d':0,'c':'unused'},
......@@ -486,59 +486,68 @@ DDRC_DEFS={ #not all fields are defined currently
# Slice1: fifo_we_ratio_slice_1[10:0] = {Reg_6B[10:9],Reg_6A[18:10]}
# Slice2: fifo_we_ratio_slice_2[10:0] = {Reg_6C[11:9],Reg_6B[18:11]}
# Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,Reg_6C[18:12]}
#seems that Reg_6C is actually Reg_6D, Reg_6B should be Reg_6C, so:
# Slice 0: fifo_we_ratio_slice_0[10:0] = {Reg_6A[9],Reg_69[18:9]}
# Slice1: fifo_we_ratio_slice_1[10:0] = {Reg_6C[10:9],Reg_6A[18:10]}
# Slice2: fifo_we_ratio_slice_2[10:0] = {Reg_6D[11:9],Reg_6C[18:11]}
# Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,Reg_6D[18:12]}
'reg_69': {'OFFS': 0x1A4,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 0','FIELDS':{
'phy_reg_status_fifo_w e_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
'reg_6a': {'OFFS': 0x1A8,'DFLT':0x000F0000,'RW':'R','FIELDS':{
'phy_reg_status_fifo_w e_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
'reg_6b': {'OFFS': 0x1AC,'DFLT':0x000F0000,'RW':'R','FIELDS':{ #may be different bits/default values
'phy_reg_status_fifo_w e_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
'phy_reg_status_fifo_we_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
'reg_6a': {'OFFS': 0x1A8,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 1','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
# 'reg_6b': {'OFFS': 0x1AC,'DFLT':0x000F0000,'RW':'R','FIELDS':{ #may be different bits/default values
# 'phy_reg_status_fifo_we_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
# 'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
# 'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
# u32 reserved8[1]; /* 0x1AC */
'reg_6c': {'OFFS': 0x1B0,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 2','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'phy_reg_bist_err': {'r':( 0, 8),'d':0, 'm':'R','c':'Mismatch error from BIST checker, 1 bit per data slice'}}},
'reg_6d': {'OFFS': 0x1B4,'DFLT':0x000F0000,'RW':'R','FIELDS':{
'reg_6d': {'OFFS': 0x1B4,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 3','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
'phy_reg_bist_err': {'r':( 0, 8),'d':0, 'm':'R','c':'Mismatch error from BIST checker, 1 bit per data slice'}}},
'reg_6e': {'OFFS': 0x1B8,'RW':'R','COMMENTS':'Training results for data slice 0','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_rdlvl_fifowein_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_bist_err': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'phy_reg_rdlvl_dqs_ratio': {'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_wrlvl_dq_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_wrlvl_dqs_ratio': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'reg_6f': {'OFFS': 0x1BC,'RW':'R','COMMENTS':'Training results for data slice 1','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_rdlvl_fifowein_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_bist_err': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'phy_reg_rdlvl_dqs_ratio': {'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_wrlvl_dq_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_wrlvl_dqs_ratio': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'reg_70': {'OFFS': 0x1C0,'RW':'R','COMMENTS':'Training results for data slice 2','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_rdlvl_fifowein_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_bist_err': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'phy_reg_rdlvl_dqs_ratio': {'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_wrlvl_dq_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_wrlvl_dqs_ratio': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'reg_71': {'OFFS': 0x1C4,'RW':'R','COMMENTS':'Training results for data slice 3','FIELDS':{
'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_rdlvl_fifowein_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_bist_err': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
'phy_reg_rdlvl_dqs_ratio': {'r':(20,29),'d':0, 'm':'R','c':'Ratio generated by Read Data Eye training'},
'phy_reg_wrlvl_dq_ratio': {'r':(10,19),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write data'},
'phy_reg_wrlvl_dqs_ratio': {'r':( 0, 9),'d':0, 'm':'R','c':'Ratio generated by Write Leveling for write DQS'}}},
# u32 reserved9[1]; /* 0x1C8 */
'phy_dll_sts0': {'OFFS': 0x1CC,'DFLT':0x00000000,'RW':'R','COMMENTS':'Slave DLL results for data slice 0','FIELDS':{
'phy_reg_status_wr_dqs_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Delay for write DQS slave DLL'},
'phy_reg_status_wr_dat a_slave_dll_value':{'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_wr_data_slave_dll_value': {'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_rd_dqs_slave_dll_value': {'r':( 0, 8),'d':0, 'm':'R','c':'Delay for read data slave DLL'}}},
'phy_dll_sts1': {'OFFS': 0x1D0,'DFLT':0x00000000,'RW':'R','COMMENTS':'Slave DLL results for data slice 1','FIELDS':{
'phy_reg_status_wr_dqs_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Delay for write DQS slave DLL'},
'phy_reg_status_wr_dat a_slave_dll_value':{'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_wr_data_slave_dll_value': {'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_rd_dqs_slave_dll_value': {'r':( 0, 8),'d':0, 'm':'R','c':'Delay for read data slave DLL'}}},
'phy_dll_sts2': {'OFFS': 0x1D4,'DFLT':0x00000000,'RW':'R','COMMENTS':'Slave DLL results for data slice 2','FIELDS':{
'phy_reg_status_wr_dqs_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Delay for write DQS slave DLL'},
'phy_reg_status_wr_dat a_slave_dll_value':{'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_wr_data_slave_dll_value': {'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_rd_dqs_slave_dll_value': {'r':( 0, 8),'d':0, 'm':'R','c':'Delay for read data slave DLL'}}},
'phy_dll_sts3': {'OFFS': 0x1D8,'DFLT':0x00000000,'RW':'R','COMMENTS':'Slave DLL results for data slice 3','FIELDS':{
'phy_reg_status_wr_dqs_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Delay for write DQS slave DLL'},
'phy_reg_status_wr_dat a_slave_dll_value':{'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_wr_data_slave_dll_value': {'r':( 9,17),'d':0, 'm':'R','c':'Delay for write data slave DLL'},
'phy_reg_status_rd_dqs_slave_dll_value': {'r':( 0, 8),'d':0, 'm':'R','c':'Delay for read data slave DLL'}}},
# u32 reserved10[1]; /* 0x1DC */
'dll_lock_sts': {'OFFS': 0x1E0,'DFLT':0x00000000,'RW':'R','COMMENTS':'DLL lock status','FIELDS':{
......@@ -553,6 +562,7 @@ DDRC_DEFS={ #not all fields are defined currently
'phy_reg_status_phy_ctrl_dll_lock': {'r':(19,19),'d':0, 'm':'R','c':'PHY control Master DLL locked'},
'phy_reg_status_of_out_delay_value': {'r':(10,18), 'm':'R','c':'Master DLL output filter output: 10:11 - fine, 12:18 - coarse'},
'phy_reg_status_of_in_delay_value': {'r':( 0, 9), 'm':'R','c':'Master DLL output filter input: 10:11 - fine, 12:18 - coarse'}}},
'phy_ctrl_sts_reg2': {'OFFS': 0x1E8,'DFLT':0x00000000,'RW':'R','COMMENTS':'PHY control status 2','FIELDS':{
'phy_reg_status_phy_ctrl_slave_dll_value': {'r':(18,26),'d':0, 'm':'R','c':'Read DQS slave DLL input'},
'reserved': {'r':( 9,17),'d':0, 'm':'R','c':'reserved'},
......
ezynq_ddrcfg_defs.py
View file @ 435a11b3
......@@ -79,7 +79,69 @@ DDR_CFG_DEFS=[
'DESCRIPTION':'Drive strength negative for driving DDR DQ/DQS signals'},
{'NAME':'BIDIR_DRIVE_POS', 'CONF_NAME':'CONFIG_EZYNQ_DDR_BIDIR_DRIVE_POS','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':28,
'DESCRIPTION':'Slew rate positive for driving DDR DQ/DQS signals'},
###### Board Dependent (to be calculated) ######
{'NAME':'PHY_WRLV_INIT_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for write leveling FSM, slice 0'},
{'NAME':'PHY_WRLV_INIT_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for write leveling FSM, slice 1'},
{'NAME':'PHY_WRLV_INIT_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for write leveling FSM, slice 2'},
{'NAME':'PHY_WRLV_INIT_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for write leveling FSM, slice 3'},
{'NAME':'PHY_GTLV_INIT_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for gate leveling FSM, slice 0'},
{'NAME':'PHY_GTLV_INIT_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for gate leveling FSM, slice 1'},
{'NAME':'PHY_GTLV_INIT_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for gate leveling FSM, slice 2'},
{'NAME':'PHY_GTLV_INIT_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Initial ratio for gate leveling FSM, slice 3'},
{'NAME':'PHY_RD_DQS_SLAVE_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for read DQS slave DLL (256 - clock period), slice 0'},
{'NAME':'PHY_RD_DQS_SLAVE_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for read DQS slave DLL (256 - clock period), slice 1'},
{'NAME':'PHY_RD_DQS_SLAVE_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for read DQS slave DLL (256 - clock period), slice 2'},
{'NAME':'PHY_RD_DQS_SLAVE_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for read DQS slave DLL (256 - clock period), slice 3'},
{'NAME':'PHY_WR_DQS_SLAVE_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Ratio for write DQS slave DLL (256 - clock period), slice 0'},
{'NAME':'PHY_WR_DQS_SLAVE_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Ratio for write DQS slave DLL (256 - clock period), slice 1'},
{'NAME':'PHY_WR_DQS_SLAVE_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Ratio for write DQS slave DLL (256 - clock period), slice 2'},
{'NAME':'PHY_WR_DQS_SLAVE_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Ratio for write DQS slave DLL (256 - clock period), slice 3'},
{'NAME':'PHY_FIFO_WE_SLAVE_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for FIFO WE slave DLL (256 - clock period), slice 0'},
{'NAME':'PHY_FIFO_WE_SLAVE_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for FIFO WE slave DLL (256 - clock period), slice 1'},
{'NAME':'PHY_FIFO_WE_SLAVE_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for FIFO WE slave DLL (256 - clock period), slice 2'},
{'NAME':'PHY_FIFO_WE_SLAVE_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x35,
'DESCRIPTION':'Ratio for FIFO WE slave DLL (256 - clock period), slice 3'},
{'NAME':'PHY_WR_DATA_SLAVE_RATIO_0', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_0','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x40,
'DESCRIPTION':'Ratio for write data slave DLL (256 - clock period), slice 0'},
{'NAME':'PHY_WR_DATA_SLAVE_RATIO_1', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_1','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x40,
'DESCRIPTION':'Ratio for write data slave DLL (256 - clock period), slice 1'},
{'NAME':'PHY_WR_DATA_SLAVE_RATIO_2', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_2','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x40,
'DESCRIPTION':'Ratio for write data slave DLL (256 - clock period), slice 2'},
{'NAME':'PHY_WR_DATA_SLAVE_RATIO_3', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_3','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x40,
'DESCRIPTION':'Ratio for write data slave DLL (256 - clock period), slice 3'},
{'NAME':'PHY_CTRL_SLAVE_RATIO', 'CONF_NAME':'CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO','TYPE':'I','MANDATORY':True,'DERIVED':False,'DEFAULT':0x80,
'DESCRIPTION':'Ratio for address/command (256 - clock period)'},
{'NAME':'PHY_INVERT_CLK', 'CONF_NAME':'CONFIG_EZYNQ_PHY_INVERT_CLK','TYPE':'B','MANDATORY':True,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Invert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS)'},
{'NAME':'SILICON', 'CONF_NAME':'CONFIG_EZYNQ_SILICON','TYPE':'T','MANDATORY':True,'DERIVED':False,'DEFAULT':'3',
'DESCRIPTION':'Zynq silicon revision'},
###### DDR Datasheet #######
{'NAME':'PARTNO', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_PARTNO','TYPE':'T','MANDATORY':True,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Memory part number (currently not used - derive some parameters later)'},
......@@ -137,8 +199,8 @@ DDR_CFG_DEFS=[
'DESCRIPTION':'MODE REGISTER SET update delay (in tCK)'},
{'NAME':'T_MOD', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_T_MOD','TYPE':'F','MANDATORY':False,'DERIVED':False,'DEFAULT':15.0,
'DESCRIPTION':'MODE REGISTER SET update delay (ns).'},
{'NAME':'T_WLMRD', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_T_WLMRD','TYPE':'F','MANDATORY':False,'DERIVED':False,'DEFAULT':40.0,
'DESCRIPTION':'Write leveling : time to the first DQS rising edge (ns).'},
{'NAME':'WLMRD', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_WLMRD','TYPE':'I','MANDATORY':False,'DERIVED':False,'DEFAULT':40,
'DESCRIPTION':'Write leveling : time to the first DQS rising edge (cycles).'},
{'NAME':'CKE', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_CKE','TYPE':'I','MANDATORY':False,'DERIVED':False,'DEFAULT':3,
'DESCRIPTION':'CKE min pulse width (in tCK)'},
{'NAME':'T_CKE', 'CONF_NAME':'CONFIG_EZYNQ_DDR_DS_T_CKE','TYPE':'F','MANDATORY':False,'DERIVED':False,'DEFAULT':7.5,
......@@ -182,7 +244,7 @@ DDR_CFG_DEFS=[
# CONFIG_EZYNQ_DDR_DS_RRD = 4
# CONFIG_EZYNQ_DDR_DS_T_RRD = 10.0
# CONFIG_EZYNQ_DDR_DS_MRD = 4
# CONFIG_EZYNQ_DDR_DS_T_WLMRD = 40.0 #
# CONFIG_EZYNQ_DDR_DS_WLMRD = 40 #
# CONFIG_EZYNQ_DDR_DS_T_MOD = 15.0
# CONFIG_EZYNQ_DDR_DS_MOD = 12
......
ezynq_ddriob_def.py
View file @ 435a11b3
......@@ -181,7 +181,7 @@ DDRIOB_DEFS={ #not all fields are defined currently
'nref_opt4': {'r':(11,13),'d':0, 'c':'DCI Calibration mode - use values in the Calibration Table'}, #1
'nref_opt2': {'r':( 8,10),'d':0, 'c':'DCI Calibration mode - use values in the Calibration Table'},
'nref_opt1': {'r':( 6, 7),'d':0, 'c':'DCI Calibration mode - use values in the Calibration Table'},
'vrn_out': {'r':( 5, 5),'d':1, 'c':'Reserved'}, #1
'vrn_out': {'r':( 5, 5),'d':1, 'c':'1 for silicon 1,2; unused (0) for silicon 3'}, #1
'vrp_out': {'r':( 4, 4),'d':0, 'c':'Reserved'},
'vrn_tri': {'r':( 3, 3),'d':0, 'c':'Reserved'},
'vrp_tri': {'r':( 2, 2),'d':0, 'c':'Reserved'},
......
ezynq_feature_config.py
View file @ 435a11b3
......@@ -121,10 +121,13 @@ class EzynqFeatures:
else:
raise Exception(self.ERRORS['ERR_NOT_AN_INTEGER']+': '+line['VALUE'] +' is not a valid INTEGER value for parameter '+ conf_name)
elif (feature['TYPE']=='F'):
try:
value= float(value)
except:
raise Exception(self.ERRORS['ERR_NOT_A_FLOAT']+': '+line['VALUE'] +' is not a valid FLOAT value for parameter '+ conf_name)
if value == 'Y':
value=1.0
else:
try:
value= float(value)
except:
raise Exception(self.ERRORS['ERR_NOT_A_FLOAT']+': '+line['VALUE'] +' is not a valid FLOAT value for parameter '+ conf_name)
elif (feature['TYPE']=='B'):
if value in self.BOOLEANS[1]:
value=True
......@@ -136,6 +139,8 @@ class EzynqFeatures:
raise Exception(self.ERRORS['ERR_NOT_A_BOOLEAN']+': '+line['VALUE'] +' is not a valid boolean value for parameter '+ conf_name+
'. Valid for "True" are:'+str(self.BOOLEANS[1])+', for "False" - '+str(self.BOOLEANS[0]))
elif (feature['TYPE']=='T'):
if value == 'Y':
value='1'
pass #keep string value
self.pars[name]=value
self.defined.add(name)
......@@ -313,8 +318,12 @@ class EzynqFeatures:
# print value
if row_class=="odd": row_class="even"
else: row_class="odd"
if (feature['TYPE']=='H') and isinstance(feature['DEFAULT'],int) and (feature['DEFAULT']>9):
sDefault=hex(feature['DEFAULT'])
else:
sDefault=str(feature['DEFAULT'])
html_file.write('<tr class="'+row_class+'"><td><b>'+feature['CONF_NAME']+'</b></td><td>'+str(value)+'</td><td>'+par_type+
'</td><td>'+('-','Y')[feature['MANDATORY']]+'</td><td>'+origin+'</td><td>'+str(feature['DEFAULT'])+'</td><td>'+feature['DESCRIPTION']+'</td></tr>\n')
'</td><td>'+('-','Y')[feature['MANDATORY']]+'</td><td>'+origin+'</td><td>'+sDefault+'</td><td>'+feature['DESCRIPTION']+'</td></tr>\n')
html_file.write('</table>\n')
\ No newline at end of file
ezynq_uart.py
View file @ 435a11b3
......@@ -106,7 +106,8 @@ class EzynqUART:
uart_extra_set= ezynq_registers.EzynqRegisters(self.UART_DEFS,self.channel,[])
# wait transmitter FIFO empty (use before proceeding to risky of reboot code )
uart_extra_set.wait_reg_field_values('channel_sts', # Channel status
(('tempty', 1)), True) # Transmitter FIFO empty (continuous)
(('tempty', 1),
('tactive', 0)), True) # Transmitter FIFO empty (continuous)
uart_extra_set.flush() # to separate codes, not to combine in one write
# wait transmitter FIFO not full (OK to put more characters)
uart_extra_set.wait_reg_field_values('channel_sts', # Channel status
......
ezynq_uboot.py
View file @ 435a11b3
......@@ -22,6 +22,7 @@ __maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
import os
import ezynq_ddrc_defs
#import ezynq_clk
import ezynq_feature_config
#Use 'TYPE':'I' for decimal output, 'H' - for hex. On input both are accepted
......@@ -38,10 +39,30 @@ UBOOT_CFG_DEFS=[
'DESCRIPTION':'Dump SLCR registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)'},
{'NAME':'DUMP_DDRC_EARLY', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_DDRC_EARLY','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Dump DDRC registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)'},
{'NAME':'DUMP_SLCR_LATE', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_SLCR_LATE','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
{'NAME':'DUMP_SLCR_LATE', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_SLCR_LATE','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Dump SLCR registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)'},
{'NAME':'DUMP_DDRC_LATE', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_DDRC_LATE','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)'},
{'NAME':'DUMP_DDRC_LATE', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_DDRC_LATE','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG)'},
{'NAME':'DUMP_TRAINING_EARLY','CONF_NAME':'CONFIG_EZYNQ_DUMP_TRAINING_EARLY','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Dump Training results before DDRC initialization (depends on CONFIG_EZYNQ_BOOT_DEBUG)'},
{'NAME':'DUMP_TRAINING_LATE', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_TRAINING_LATE','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':True,
'DESCRIPTION':'Dump Training results after DDRC initialization (depends on CONFIG_EZYNQ_BOOT_DEBUG)'},
{'NAME':'DUMP_OCM', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_OCM','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Dump OCM memory range'},
{'NAME':'DUMP_DDR', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_DDR','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':False,
'DESCRIPTION':'Dump DDER memory range'},
{'NAME':'DUMP_OCM_LOW', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_OCM_LOW','TYPE':'H','MANDATORY':False,'DERIVED':False,'DEFAULT':0,
'DESCRIPTION':'Dump OCM memory range start address'},
{'NAME':'DUMP_OCM_HIGH', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_OCM_HIGH','TYPE':'H','MANDATORY':False,'DERIVED':False,'DEFAULT':0x2ff,
'DESCRIPTION':'Dump OCM memory range end address'},
{'NAME':'DUMP_DDR_LOW', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_DDR_LOW','TYPE':'H','MANDATORY':False,'DERIVED':False,'DEFAULT':0x4000000,
'DESCRIPTION':'Dump DDR memory range start address'},
{'NAME':'DUMP_DDR_HIGH', 'CONF_NAME':'CONFIG_EZYNQ_DUMP_DDR_HIGH','TYPE':'H','MANDATORY':False,'DERIVED':False,'DEFAULT':0x40002ff,
'DESCRIPTION':'Dump DDR memory range end address'},
{'NAME':'LED_CHECKPOINT_1', 'CONF_NAME':'CONFIG_EZYNQ_LED_CHECKPOINT_1', 'TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':None,
'DESCRIPTION':'LED ON/OFF in RBL (just after MIO is set up)'},
......@@ -403,11 +424,154 @@ inline void ddrc_wait_queue_empty(void)
if led_cp:
self.cfile+='\tdebug_led_on(); /* Turn debug LED ON */\n'
else:
self.cfile+='\tdebug_led_off(); /* Turn debug LED OFF */\n'
def make_arch_cpu_init (self):
self.cfile+='\tdebug_led_off(); /* Turn debug LED OFF */\n'
def _read_bit_field(self,reg_set,reg_name,field_name,channel=0): #accepts bit field tuple instead of the field name
addr=reg_set['BASE_ADDR'][channel]+ reg_set[reg_name]['OFFS']
if isinstance(field_name,tuple):
bits = field_name
else:
bits= reg_set[reg_name]['FIELDS'][field_name]['r']
# self._report_bit_field('BIST errors from reg_6c (1 bit per slice)',DDRC_DEFS,'reg_6c','phy_reg_bist_err')
mask=(1<<(max(bits)-min(bits)))-1
return ('(readl(0x%08x) >> %d) & 0x%x'%(addr,min(bits),mask), max(bits)-min(bits))
def _report_bit_field(self,name,reg_set,reg_name,field_name,channel=0):
self.cfile+='\tuart_puts("'+name+' = 0x");\n'
self.cfile+='\tuart_put_hex('+self._read_bit_field(reg_set,reg_name,field_name,channel)[0]+');\n'
self.cfile+='\tuart_puts("\\r\\n");\n'
def _report_multi_bit_fields(self,name,reg_set,fields,channel=0):
expr=''
shft=0
for field in reversed(fields):
e,w=self._read_bit_field(reg_set,field[0],field[1],channel)
if shft==0:
expr+='('+e+')'
else:
expr+='+(('+e+') << '+str(shft)+')'
shft+=w
self.cfile+='\tuart_puts("'+name+' = 0x");\n'
self.cfile+='\tuart_put_hex('+expr+');\n'
self.cfile+='\tuart_puts("\\r\\n");\n'
def make_report_training(self):
if not (self.features.get_par_value_or_none('DUMP_TRAINING_EARLY') or self.features.get_par_value_or_none('DUMP_TRAINING_LATE') ):
return # do not generate any code
DDRC_DEFS= ezynq_ddrc_defs.DDRC_DEFS
self.cfile+='''/* Report DDR training results*/
void report_training(void)
{
'''
# The fifo_we_slave ratios for each slice(0 through 3) must be interpreted by software in the following way:
# Slice 0: fifo_we_ratio_slice_0[10:0] = {Reg_6A[9],Reg_69[18:9]}\
# There is no Reg_B !!!
# Slice1: fifo_we_ratio_slice_1[10:0] = {Reg_6B[10:9],Reg_6A[18:10]}
# Slice2: fifo_we_ratio_slice_2[10:0] = {Reg_6C[11:9],Reg_6B[18:11]}
# Slice3: fifo_we_ratio_slice_3[10:0] = {phy_reg_rdlvl_fifowein_ratio_slice3_msb,Reg_6C[18:12]}
# 'reg_69': {'OFFS': 0x1A4,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 0','FIELDS':{
# 'phy_reg_status_fifo_we_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
# 'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
# 'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
# 'reg_6a': {'OFFS': 0x1A8,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 1','FIELDS':{
# 'phy_reg_status_fifo_we_slave_dll_value': {'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
# 'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
# 'reserved': {'r':( 0, 8),'d':0, 'm':'R','c':'reserved'}}},
# # u32 reserved8[1]; /* 0x1AC */
# 'reg_6c': {'OFFS': 0x1B0,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 2','FIELDS':{
# 'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
# 'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
# 'phy_reg_bist_err': {'r':( 0, 8),'d':0, 'm':'R','c':'Mismatch error from BIST checker, 1 bit per data slice'}}},
# 'reg_6d': {'OFFS': 0x1B4,'DFLT':0x000F0000,'RW':'R','COMMENTS':'Training results for data slice 3','FIELDS':{
# 'phy_reg_status_fifo_we_slave_dll_value':{'r':(20,28),'d':0, 'm':'R','c':'Delay of FIFO WE slave DLL'},
# 'phy_reg_rdlvl_fifowein_ratio': {'r':( 9,19),'d':0x780,'m':'R','c':'Ratio by Read Gate training FSM'},
# 'phy_reg_bist_err': {'r':( 0, 8),'d':0, 'm':'R','c':'Mismatch error from BIST checker, 1 bit per data slice'}}},
self._report_bit_field('BIST errors from reg_6c (1 bit per slice)',DDRC_DEFS,'reg_6c','phy_reg_bist_err')
self._report_bit_field('BIST errors from reg_6d (1 bit per slice)',DDRC_DEFS,'reg_6d','phy_reg_bist_err')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('FIFO WE DLL SLICE 0',DDRC_DEFS,'reg_69','phy_reg_status_fifo_we_slave_dll_value')
self._report_bit_field('FIFO WE DLL SLICE 1',DDRC_DEFS,'reg_6a','phy_reg_status_fifo_we_slave_dll_value')
self._report_bit_field('FIFO WE DLL SLICE 2',DDRC_DEFS,'reg_6c','phy_reg_status_fifo_we_slave_dll_value')
self._report_bit_field('FIFO WE DLL SLICE 3',DDRC_DEFS,'reg_6d','phy_reg_status_fifo_we_slave_dll_value')
self.cfile+='\tuart_puts("\\r\\n");\n'
# self._report_bit_field('Ratio from Read Gate Training SLICE 0', DDRC_DEFS,'reg_69','phy_reg_rdlvl_fifowein_ratio')
# self._report_bit_field('Ratio from Read Gate Training SLICE 1', DDRC_DEFS,'reg_6a','phy_reg_rdlvl_fifowein_ratio')
# self._report_bit_field('Ratio from Read Gate Training SLICE 2', DDRC_DEFS,'reg_6c','phy_reg_rdlvl_fifowein_ratio')
# self._report_bit_field('Ratio from Read Gate Training SLICE 3', DDRC_DEFS,'reg_6d','phy_reg_rdlvl_fifowein_ratio')
# self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_multi_bit_fields('FIFO WE ratio SLICE 0',DDRC_DEFS,(('reg_6a',( 9, 9)),('reg_69',( 9,18))))
self._report_multi_bit_fields('FIFO WE ratio SLICE 1',DDRC_DEFS,(('reg_6c',( 9,10)),('reg_6a',(10,18))))
self._report_multi_bit_fields('FIFO WE ratio SLICE 2',DDRC_DEFS,(('reg_6d',( 9,11)),('reg_6c',(11,18))))
self._report_multi_bit_fields('FIFO WE ratio SLICE 3',DDRC_DEFS,
(('dll_lock_sts','phy_reg_rdlvl_fifowein_ratio_slice3_msb'),
('reg_6d',(12,18))))
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('DQS ratio from Read Data Eye Training SLICE 0',DDRC_DEFS,'reg_6e','phy_reg_rdlvl_dqs_ratio')
self._report_bit_field('DQS ratio from Read Data Eye Training SLICE 1',DDRC_DEFS,'reg_6f','phy_reg_rdlvl_dqs_ratio')
self._report_bit_field('DQS ratio from Read Data Eye Training SLICE 2',DDRC_DEFS,'reg_70','phy_reg_rdlvl_dqs_ratio')
self._report_bit_field('DQS ratio from Read Data Eye Training SLICE 3',DDRC_DEFS,'reg_71','phy_reg_rdlvl_dqs_ratio')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('DQ write data ratio from Write Leveling Training SLICE 0',DDRC_DEFS,'reg_6e','phy_reg_wrlvl_dq_ratio')
self._report_bit_field('DQ write data ratio from Write Leveling Training SLICE 1',DDRC_DEFS,'reg_6f','phy_reg_wrlvl_dq_ratio')
self._report_bit_field('DQ write data ratio from Write Leveling Training SLICE 2',DDRC_DEFS,'reg_70','phy_reg_wrlvl_dq_ratio')
self._report_bit_field('DQ write data ratio from Write Leveling Training SLICE 3',DDRC_DEFS,'reg_71','phy_reg_wrlvl_dq_ratio')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('DQS write ratio from Write Leveling Training SLICE 0',DDRC_DEFS,'reg_6e','phy_reg_wrlvl_dqs_ratio')
self._report_bit_field('DQS write ratio from Write Leveling Training SLICE 1',DDRC_DEFS,'reg_6f','phy_reg_wrlvl_dqs_ratio')
self._report_bit_field('DQS write ratio from Write Leveling Training SLICE 2',DDRC_DEFS,'reg_70','phy_reg_wrlvl_dqs_ratio')
self._report_bit_field('DQS write ratio from Write Leveling Training SLICE 3',DDRC_DEFS,'reg_71','phy_reg_wrlvl_dqs_ratio')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('Delay for write DQS slave DLL SLICE 0',DDRC_DEFS,'phy_dll_sts0','phy_reg_status_wr_dqs_slave_dll_value')
self._report_bit_field('Delay for write DQS slave DLL SLICE 1',DDRC_DEFS,'phy_dll_sts1','phy_reg_status_wr_dqs_slave_dll_value')
self._report_bit_field('Delay for write DQS slave DLL SLICE 2',DDRC_DEFS,'phy_dll_sts2','phy_reg_status_wr_dqs_slave_dll_value')
self._report_bit_field('Delay for write DQS slave DLL SLICE 3',DDRC_DEFS,'phy_dll_sts3','phy_reg_status_wr_dqs_slave_dll_value')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('Delay for write DQ slave DLL SLICE 0',DDRC_DEFS,'phy_dll_sts0','phy_reg_status_wr_data_slave_dll_value')
self._report_bit_field('Delay for write DQ slave DLL SLICE 1',DDRC_DEFS,'phy_dll_sts1','phy_reg_status_wr_data_slave_dll_value')
self._report_bit_field('Delay for write DQ slave DLL SLICE 2',DDRC_DEFS,'phy_dll_sts2','phy_reg_status_wr_data_slave_dll_value')
self._report_bit_field('Delay for write DQ slave DLL SLICE 3',DDRC_DEFS,'phy_dll_sts3','phy_reg_status_wr_data_slave_dll_value')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('Delay for read DQ slave DLL SLICE 0',DDRC_DEFS,'phy_dll_sts0','phy_reg_status_rd_dqs_slave_dll_value')
self._report_bit_field('Delay for read DQ slave DLL SLICE 1',DDRC_DEFS,'phy_dll_sts1','phy_reg_status_rd_dqs_slave_dll_value')
self._report_bit_field('Delay for read DQ slave DLL SLICE 2',DDRC_DEFS,'phy_dll_sts2','phy_reg_status_rd_dqs_slave_dll_value')
self._report_bit_field('Delay for read DQ slave DLL SLICE 3',DDRC_DEFS,'phy_dll_sts3','phy_reg_status_rd_dqs_slave_dll_value')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('Delay all Slave DLLs for Master DLL 1',DDRC_DEFS,'dll_lock_sts','phy_reg_status_dll_slave_value_1')
self._report_bit_field('Delay all Slave DLLs for Master DLL 0',DDRC_DEFS,'dll_lock_sts','phy_reg_status_dll_slave_value_0')
self._report_bit_field('Master DLL 1 locked',DDRC_DEFS,'dll_lock_sts','phy_reg_status_dll_lock_1')
self._report_bit_field('Master DLL 0 locked',DDRC_DEFS,'dll_lock_sts','phy_reg_status_dll_lock_0')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('Master DLL Output filter locked (+2 - coarse, +1 - fine',DDRC_DEFS,'phy_ctrl_sts','phy_reg_status_phy_ctrl_of_in_lock_state')
self._report_bit_field('Values applied to PHY_CTRL Slave DLL', DDRC_DEFS,'phy_ctrl_sts','phy_reg_status_phy_ctrl_dll_slave_value')
self._report_bit_field('PHY Control Master DLL status (locked)', DDRC_DEFS,'phy_ctrl_sts','phy_reg_status_phy_ctrl_dll_lock')
self._report_bit_field('Values from Master DLL Output Filter', DDRC_DEFS,'phy_ctrl_sts','phy_reg_status_of_out_delay_value')
self._report_bit_field('Values applied to Master DLL Output Filter', DDRC_DEFS,'phy_ctrl_sts','phy_reg_status_of_in_delay_value')
self.cfile+='\tuart_puts("\\r\\n");\n'
self._report_bit_field('Delay values applied to read DQS slave DLL', DDRC_DEFS,'phy_ctrl_sts_reg2','phy_reg_status_phy_ctrl_slave_dll_value')
self._report_bit_field('Values applied to Master DLL Output Filter', DDRC_DEFS,'phy_ctrl_sts_reg2','phy_reg_status_phy_ctrl_of_in_delay_value')
self.cfile+='}\n'
self.sections.append('ddrc_training')
def make_arch_cpu_init(self):
self.cfile+='''/* Initialize clocks, DDR memory, copy OCM to DDR */
int arch_cpu_init(void)
{
......@@ -430,6 +594,13 @@ int arch_cpu_init(void)
self._cp_led('LED_CHECKPOINT_4') # After PLL bypass is OFF
if 'uart_init' in self.sections:
self.cfile+='\tuart_init(); /* Initialize UART for debug information output */\n'
self.cfile+='\tuart_puts("devcfg.PS_VERSION=");\n'
self.cfile+='\tuart_put_hex(readl(0xf8007080));\n'; #TODO:Compare against specified
self.cfile+='\tuart_puts("\\r\\n");\n'
self.cfile+='\tuart_puts("slcr.PSS_IDCODE=");\n'
self.cfile+='\tuart_put_hex(readl(0xf8000530));\n';
self.cfile+='\tuart_puts("\\r\\n");\n'
self._cp_led('LED_CHECKPOINT_5') # After UART is programmed
if self.features.get_par_value_or_none('DUMP_SLCR_EARLY'):
self.cfile+='\tuart_puts("SLCR registers before DCI/DDR initialization\\r\\n");\n'
......@@ -437,8 +608,15 @@ int arch_cpu_init(void)
if self.features.get_par_value_or_none('DUMP_DDRC_EARLY'):
self.cfile+='\tuart_puts("DDRC registers before DCI/DDR initialization\\r\\n");\n'
self.cfile+='\tdump_ddrc_regs(); /* Dump all DDRC registers before DCI/DDR initialization */\n'
if self.features.get_par_value_or_none('DUMP_TRAINING_EARLY'):
self.cfile+='\tuart_puts("Training results registers state before DDRC initialization\\r\\n");\n'
self.cfile+='\treport_training(); /* Print training results */\n'
# if 'uart_xmit' in self.sections:
# self.cfile+='\tuart_wait_tx_fifo_empty();\n'
self.cfile+='\tdci_calibration(); /* Calibrate DDR DCI impedance and wait for completion */\n'
self._cp_led('LED_CHECKPOINT_6') # After DCI is calibrated
# self._cp_led('LED_CHECKPOINT_6') # After DCI is calibrated
self.cfile+='\tddr_start(); /* Remove soft reset from DDR controller - this will start initialization. Wait for completion */\n'
self._cp_led('LED_CHECKPOINT_7') # After DDR is initialized
if self.features.get_par_value_or_none('DUMP_SLCR_LATE'):
......@@ -447,6 +625,9 @@ int arch_cpu_init(void)
if self.features.get_par_value_or_none('DUMP_DDRC_LATE'):
self.cfile+='\tuart_puts("DDRC registers after DCI/DDR initialization\\r\\n");\n'
self.cfile+='\tdump_ddrc_regs(); /* Dump all DDRC registers after DCI/DDR initialization */\n'
if self.features.get_par_value_or_none('DUMP_TRAINING_LATE'):
self.cfile+='\tuart_puts("Training results registers state after DDRC initialization\\r\\n");\n'
self.cfile+='\treport_training(); /* Print training results */\n'
self.cfile+='''/* Copy 3 pages of OCM from 0x00000.0x2ffff to DDR 0x4000000.0x402ffff*/
\tint * s= (int *) 0;
\tint * d= (int *) 0x4000000;
......@@ -455,6 +636,20 @@ int arch_cpu_init(void)
self.cfile+='\tddrc_wait_queue_empty(); /* Wait no commands are pending in DDRC queue */\n'
self._cp_led('LED_CHECKPOINT_8') # Before relocation to DDR (to 0x4000000+ )
if self.features.get_par_value_or_none('DUMP_OCM'):
self.cfile+='\tuart_puts("OCM memory data\\r\\n");\n'
self.cfile+='\tuart_dump_regs(0x%08x,0x%08x, 16);\n'%(self.features.get_par_value_or_default('DUMP_OCM_LOW'),self.features.get_par_value_or_default('DUMP_OCM_HIGH'))
self.cfile+='\tuart_puts("\\r\\n");\n'
if self.features.get_par_value_or_none('DUMP_DDR'):
self.cfile+='\tuart_puts("DDR memory data\\r\\n");\n'
self.cfile+='\tuart_dump_regs(0x%08x,0x%08x, 16);\n'%(self.features.get_par_value_or_default('DUMP_DDR_LOW'),self.features.get_par_value_or_default('DUMP_DDR_HIGH'))
self.cfile+='\tuart_puts("\\r\\n");\n'
# if 'uart_xmit' in self.sections:
# self.cfile+='\tuart_wait_tx_fifo_empty();\n'
self.cfile+='''/*
Now jump to the same instruction in the DDR copy of the currently executed code in OCM
Be careful not to call functions or access data stored in the 3 lower OCM pages.
......@@ -505,6 +700,27 @@ int arch_cpu_init(void)
\twritel(0xC, &slcr_base->ddr_urgent);
'''
if 'uart_xmit' in self.sections:
self.cfile+='\tuart_put_hex(readl(0xe000002c));\n'
self.cfile+='\tuart_putc(0xd);\n'
self.cfile+='\tuart_putc(0xa);\n'
self.cfile+='\tuart_put_hex(readl(0xe000002c));\n'
self.cfile+='\tuart_putc(0xd);\n'
self.cfile+='\tuart_putc(0xa);\n'
# self.cfile+='\twhile((readl(0xe000002c) & 0x808) != 8); /* uart0.channel_sts Channel status */\n'
self.cfile+='\tuart_put_hex(readl(0xe000002c));\n'
self.cfile+='\tuart_putc(0xd);\n'
self.cfile+='\tuart_putc(0xa);\n'
self.cfile+='\tuart_put_hex(readl(0xe000002c));\n'
self.cfile+='\tuart_putc(0xd);\n'
self.cfile+='\tuart_putc(0xa);\n'
self.cfile+='\tuart_put_hex(0x12345678);\n'
self.cfile+='\tuart_putc(0xd);\n'
self.cfile+='\tuart_putc(0xa);\n'
self.cfile+='\tuart_put_hex(0x12345678);\n'
self.cfile+='\tuart_putc(0xd);\n'
self.cfile+='\tuart_putc(0xa);\n'
self.cfile+='\twhile((readl(0xe000002c) & 0x808) != 8); /* uart0.channel_sts Channel status */\n'
self.cfile+='\tuart_wait_tx_fifo_empty(); /* u-boot may re-program UART differently, wait all is sent before getting there */\n'
#uart_wait_tx_fifo_empty() - add if u-boot debug is on
self._cp_led('LED_CHECKPOINT_12') # Before leaving lowlevel_init()
......@@ -513,6 +729,7 @@ int arch_cpu_init(void)
if 'gpio_out' in self.sections:
self.cfile+='\tsetup_gpio_outputs(); /* Setup GPIO outputs */\n'
#LOCK_SLCR
if self.features.get_par_value_or_none('LOCK_SLCR') is False:
self.cfile+='/* Leaving SLCR registers UNLOCKED according to setting of %s */\n'%self.features.get_par_confname('LOCK_SLCR')
......
ezynqcfg.py
View file @ 435a11b3
......@@ -576,6 +576,7 @@ if (args.lowlevel):
u_boot.uart_transmit (reg_sets[segment_dict['UART_XMIT']['FROM']:segment_dict['UART_XMIT']['TO']])
u_boot.make_ddrc_register_dump()
u_boot.make_slcr_register_dump()
u_boot.make_report_training()
#if not u_boot.features.get_par_value_or_none('BOOT_DEBUG') is None:
if 'DCI' in segment_dict:
......
test.mk
View file @ 435a11b3
......@@ -154,9 +154,9 @@ CONFIG_EZYNQ_DDR_BANK_ADDR_MAP = 10 # DRAM address mapping: number of c
CONFIG_EZYNQ_DDR_ARB_PAGE_BANK = N # Enable Arbiter prioritization based on page/bank match
CONFIG_EZYNQ_DDR_ECC = Disabled # Enable ECC for the DDR memory
CONFIG_EZYNQ_DDR_BUS_WIDTH = 32 # SoC DDR bus width
CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL =0 # Automatically train write leveling during initialization
CONFIG_EZYNQ_DDR_TRAIN_READ_GATE = 0 # Automatically train read gate timing during initialization
CONFIG_EZYNQ_DDR_TRAIN_DATA_EYE = 0 # Automatically train data eye during initialization
CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL =1 # Automatically train write leveling during initialization
CONFIG_EZYNQ_DDR_TRAIN_READ_GATE = 1 # Automatically train read gate timing during initialization
CONFIG_EZYNQ_DDR_TRAIN_DATA_EYE = 1 # Automatically train data eye during initialization
CONFIG_EZYNQ_DDR_CLOCK_STOP_EN = 0 # Enable clock stop
CONFIG_EZYNQ_DDR_USE_INTERNAL_VREF =0 # Use internal Vref
......@@ -207,9 +207,9 @@ CONFIG_EZYNQ_DDR_DS_T_RRD 10.0 # ACTIVATE-to-ACTIVATE minimal command
CONFIG_EZYNQ_DDR_DS_MRD = 4 # MODE REGISTER SET command period (in tCK)
CONFIG_EZYNQ_DDR_DS_MOD = 12 # MODE REGISTER SET update delay (in tCK)
CONFIG_EZYNQ_DDR_DS_T_MOD = 15.0 # MODE REGISTER SET update delay (ns).
CONFIG_EZYNQ_DDR_DS_T_WLMRD = 40.0 # Write leveling : time to the first DQS rising edge (ns).
CONFIG_EZYNQ_DDR_DS_WLMRD = 40 # Write leveling : time to the first DQS rising edge (cycles).
CONFIG_EZYNQ_DDR_DS_CKE = 3 # CKE min pulse width (in tCK)
CONFIG_EZYNQ_DDR_DS_T_CKE = 7.5 # CKE min pulse width (ns). # 5.625
CONFIG_EZYNQ_DDR_DS_T_CKE = 5.625 # CKE min pulse width (ns). # 7.5
CONFIG_EZYNQ_DDR_DS_CKSRE = 5 # Keep valid clock after self refresh/power down entry (in tCK)
CONFIG_EZYNQ_DDR_DS_T_CKSRE = 10.0 # Keep valid clock after self refresh/power down entry (ns).
CONFIG_EZYNQ_DDR_DS_CKSRX = 5 # Valid clock before self refresh, power down or reset exit (in tCK)
......
u-boot-tree/boards.cfg
View file @ 435a11b3
......@@ -1183,5 +1183,7 @@ gr_ep2s60 sparc leon3 - gaisler
grsim sparc leon3 - gaisler
gr_xc3s_1500 sparc leon3 - gaisler
coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000
elphel393 arm armv7 elphel393 elphel zynq
# Target ARCH CPU Board name Vendor SoC Options
########################################################################################################################
u-boot-tree/include/configs/elphel393.h 0 → 100644
View file @ 435a11b3
/*
* (C) Copyright 2012 Xilinx
* (C) Copyright 2013 Elphel
*
* Configuration for Elphel393 Board
* See zynq_common.h for Zynq common configs
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_ELPHEL393_H
#define __CONFIG_ELPHEL393_H
/*#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) */
#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART0 *
#if 0
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#endif
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0
//#define CONFIG_ZYNQ_SPI
/* #define CONFIG_NAND_ZYNQ */
/* With NAND 0x31048. no memtest - 0x30d20, undef CONFIG_CMDLINE_EDITING - 0x30468 */
#undef CONFIG_SYS_TEXT_BASE
#include <configs/zynq_common.h>
#include <configs/ezynq/ezynq_MT41K256M16HA107.h> /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
#include <configs/ezynq/ezynq_XC7Z030_1FBG484C.h>
#include <configs/ezynq/ezynq393.h>
#define CONFIG_CMD_MEMTEST
/* twice slower */
#undef CONFIG_ZYNQ_SERIAL_CLOCK0
/*#define CONFIG_ZYNQ_SERIAL_CLOCK0 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK0 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_ZYNQ_SERIAL_CLOCK1
/*#define CONFIG_ZYNQ_SERIAL_CLOCK1 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK1 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_BOOTDELAY
#undef CONFIG_SYS_PROMPT
#undef CONFIG_SYS_SDRAM_BASE
#undef CONFIG_ENV_SIZE
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_BOOTDELAY -1 /* -1 to Disable autoboot */
#define CONFIG_SYS_PROMPT "elphel393> "
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Physical start address of SDRAM. _Must_ be 0 here. */
#define CONFIG_ENV_SIZE 1400
#define CONFIG_SYS_TEXT_BASE 0x00000000 //0x04000000 with 0x04000000 - does not get to the low_Level_init?
/*
#define CONFIG_EZYNQ_SKIP_DDR
*/
#define CONFIG_EZYNQ_SKIP_CLK
//undefs
/* undefs */
/*#undef CONFIG_FS_FAT */
/* #undef CONFIG_SUPPORT_VFAT */
/* #undef CONFIG_CMD_FAT */
/* http://lists.denx.de/pipermail/u-boot/2003-October/002631.html */
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
/* CONFIG_FS_FAT=y */
/* disable PL*/
#undef CONFIG_FPGA
#undef CONFIG_FPGA_XILINX
#undef CONFIG_FPGA_ZYNQPL
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_EXT2
#undef CONFIG_CMD_CACHE
#undef DEBUG
#undef CONFIG_AUTO_COMPLETE
#undef CONFIG_SYS_LONGHELP
/*#undef CONFIG_CMDLINE_EDITING */
/* redefine env settings*/
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ethaddr=00:0a:35:00:01:22\0" \
"kernel_image=uImage\0" \
"ramdisk_image=uramdisk.image.gz\0" \
"devicetree_image=devicetree.dtb\0" \
"bitstream_image=system.bit.bin\0" \
"loadbit_addr=0x100000\0" \
"kernel_size=0x500000\0" \
"devicetree_size=0x20000\0" \
"ramdisk_size=0x5E0000\0" \
"fdt_high=0x20000000\0" \
"initrd_high=0x20000000\0" \
"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
"mmcinfo && " \
"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
"fpga load 0 ${loadbit_addr} ${filesize}\0" \
"sdboot=echo Copying Linux from SD to RAM... && " \
"mmcinfo && " \
"fatload mmc 0 0x3000000 ${kernel_image} && " \
"fatload mmc 0 0x2A00000 ${devicetree_image} && " \
"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"nandboot=echo Copying Linux from NAND flash to RAM... && " \
"nand read 0x3000000 0x100000 ${kernel_size} && " \
"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
"echo Copying ramdisk... && " \
"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0"
/* */
#endif /* __CONFIG_ELPHEL393_H */
u-boot-tree/include/configs/ezynq/ezynq393.h 0 → 100644
View file @ 435a11b3
/*
* (C) Copyright 2013 Elphel, Inc.
*
* Configuration for Elphel393 hardware initialization (pre-U-Boot)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_EZYNQ_H
#define __CONFIG_EZYNQ_H
#define CONFIG_EZYNQ
/* Boot image cionfiguration parameters */
#define CONFIG_EZYNQ_BOOT_USERDEF 0x1010000 /* 0x1234567 will be saved in the file header */
#define CONFIG_EZYNQ_BOOT_OCM_OFFSET 0x8c0 /* 0xa40 0x8C0 start of OCM data relative to the flash image start > 0x8C0, 63-bytes aligned */
#define CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH 0x30000 /* 0x1400c 0x30000 number of bytes to load to the OCM memory, < 0x30000 */
#define CONFIG_EZYNQ_START_EXEC 0x00 /* start of execution address */
#define CONFIG_EZYNQ_RESERVED44 0 /* documented as 0, but actually 1 */
/* Boot debug setup */
#define CONFIG_EZYNQ_BOOT_DEBUG Y /* configure UARTx and send register dumps there.*/
#define CONFIG_EZYNQ_LOCK_SLCR OFF /* Lock SLCR registers when all is done. */
#define CONFIG_EZYNQ_DUMP_SLCR_EARLY /* Dump SLCR registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
#define CONFIG_EZYNQ_DUMP_DDRC_EARLY /* Dump DDRC registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
#define CONFIG_EZYNQ_DUMP_SLCR_LATE /* Dump SLCR registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
#define CONFIG_EZYNQ_DUMP_DDRC_LATE /* Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
#define CONFIG_EZYNQ_DUMP_TRAINING_EARLY N /* Training results registers before DDRC initialization */
#define CONFIG_EZYNQ_DUMP_TRAINING_LATE Y /* Training results registers after DDRC initialization */
#define CONFIG_EZYNQ_DUMP_OCM /* Dump (some of) OCM data */
#define CONFIG_EZYNQ_DUMP_DDR /* Dump (some of) DDR data */
#if 0
#define CONFIG_EZYNQ_DUMP_OCM_LOW 0x0 /* OCM dump start (deafault 0) */
#define CONFIG_EZYNQ_DUMP_OCM_HIGH 0x2ff /* OCM dump end (deafault 0x2ff, full - 0x2ffff) */
#define CONFIG_EZYNQ_DUMP_DDR_LOW 0x4000000 /* DDR dump start (deafault 0x4000000, start of the OCM copy) */
#define CONFIG_EZYNQ_DUMP_DDR_HIGH 0x40002ff /* DDR dump end (deafault 0x40002ff) */
#endif
/* Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG and CONFIG_EZYNQ_BOOT_DEBUG to be set
If defined, each can be 0,1, ON or OFF */
#define CONFIG_EZYNQ_LED_CHECKPOINT_1 ON /* in RBL setup, as soon as MIO is programmed */
#define CONFIG_EZYNQ_LED_CHECKPOINT_2 OFF /* First after getting to user code */
#define CONFIG_EZYNQ_LED_CHECKPOINT_3 ON /* After setting clock registers */
#define CONFIG_EZYNQ_LED_CHECKPOINT_4 OFF /* After PLL bypass is OFF */
#define CONFIG_EZYNQ_LED_CHECKPOINT_5 ON /* After UART is programmed */
#define CONFIG_EZYNQ_LED_CHECKPOINT_6 OFF /* After DCI is calibrated */
#define CONFIG_EZYNQ_LED_CHECKPOINT_7 ON /* After DDR is initialized */
#define CONFIG_EZYNQ_LED_CHECKPOINT_8 OFF /* Before relocation to DDR (to 0x4000000+ ) */
#define CONFIG_EZYNQ_LED_CHECKPOINT_9 ON /* After relocation to DDR (to 0x4000000+ ) */
#define CONFIG_EZYNQ_LED_CHECKPOINT_10 OFF /* Before remapping OCM0-OCM2 high */
#define CONFIG_EZYNQ_LED_CHECKPOINT_11 ON /* After remapping OCM0-OCM2 high */
#define CONFIG_EZYNQ_LED_CHECKPOINT_12 OFF /* Before leaving lowlevel_init() */
/* MIO configuration */
#define CONFIG_EZYNQ_OCM /* not used */
#define CONFIG_EZYNQ_MIO_0_VOLT 1.8
#define CONFIG_EZYNQ_MIO_1_VOLT 1.8
#define CONFIG_EZYNQ_NAND__SLOW
#define CONFIG_EZYNQ_MIO_ETH_0__SLOW
/*#define CONFIG_EZYNQ_MIO_ETH_MDIO__SLOW */
#define CONFIG_EZYNQ_MIO_USB_0__SLOW
#define CONFIG_EZYNQ_MIO_USB_0__PULLUP
#define CONFIG_EZYNQ_MIO_SDIO_0 40 /* 16,28,40 */
#define CONFIG_EZYNQ_MIO_SDIO_0__SLOW
#define CONFIG_EZYNQ_MIO_SDIO_0__PULLUP
#define CONFIG_EZYNQ_MIO_SDCD_0 48 /* any but 7,8 */
#define CONFIG_EZYNQ_MIO_SDCD_0__PULLUP
#define CONFIG_EZYNQ_MIO_I2C_0 50
#define CONFIG_EZYNQ_MIO_I2C_0__PULLUP
#define CONFIG_EZYNQ_MIO_UART_0 46 /* # 8+4*N */
/*
Red LED - pullup, input - on,
output (or undefined) - off
#define CONFIG_EZYNQ_MIO_PULLUP_EN_47
#define CONFIG_EZYNQ_MIO_PULLUP_DIS_0
#define CONFIG_EZYNQ_MIO_INOUT_47 OUT
#define CONFIG_EZYNQ_MIO_INOUT_47 IN
#define CONFIG_EZYNQ_MIO_INOUT_47 BIDIR
*/
/* DDR chip independent */
#define CONFIG_EZYNQ_DDR_ENABLE Y /* Enable DDR memory */
/* Only specify CONFIG_EZYNQ_DDR_FREQ_MHZ if you want the DDR frequency used for timing calculations is different from actual */
/* #define CONFIG_EZYNQ_DDR_FREQ_MHZ 533.333333 */ /* DDR clock frequency in MHz, this value overwrites the one calculated by the PLL/clock setup */
#define CONFIG_EZYNQ_DDR_BANK_ADDR_MAP 10 /* DRAM address mapping: number of combined column and row addresses lower than BA0 */
#define CONFIG_EZYNQ_DDR_ARB_PAGE_BANK N /* Enable Arbiter prioritization based on page/bank match */
#define CONFIG_EZYNQ_DDR_ECC Disabled /* Enable ECC for the DDR memory */
#define CONFIG_EZYNQ_DDR_BUS_WIDTH 32 /* SoC DDR bus width */
#define CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL 0 /* Automatically train write leveling during initialization */
#define CONFIG_EZYNQ_DDR_TRAIN_READ_GATE 0 /* Automatically train read gate timing during initialization */
#define CONFIG_EZYNQ_DDR_TRAIN_DATA_EYE 0 /* Automatically train data eye during initialization */
#define CONFIG_EZYNQ_DDR_CLOCK_STOP_EN 0 /* Enable clock stop */
#define CONFIG_EZYNQ_DDR_USE_INTERNAL_VREF 0 /* Use internal Vref */
/* DDR chip Dependent */
#define CONFIG_EZYNQ_DDR_CL 7 /* CAS read latency (in tCK) */
#define CONFIG_EZYNQ_DDR_CWL 6 /* CAS write latency (in tCK) */
#define CONFIG_EZYNQ_DDR_AL 0 /* Posted CAS additive latency (in tCK) */
#define CONFIG_EZYNQ_DDR_BL 8 /* Burst length, 16 is only supported for LPDDR2 */
#define CONFIG_EZYNQ_DDR_HIGH_TEMP False /* Normal High temperature (influences refresh) */
#define CONFIG_EZYNQ_DDR_SPEED_BIN DDR3_1066F /* Memory speed bin (currently not used - derive timing later) */
#define CONFIG_EZYNQ_DDR_DDR2_RTT 75 /* DDR2 on-chip termination, Ohm ('DISABLED','75','150','50' */
#define CONFIG_EZYNQ_DDR_DDR3_RTT 60 /* DDR3 on-chip termination, Ohm ('DISABLED','60','120','40') Does not include 20 & 30 - not clear if DDRC can use them with auto write leveling */
#define CONFIG_EZYNQ_DDR_OUT_SLEW_NEG 26 /* Slew rate negative for DDR address/clock outputs */
#define CONFIG_EZYNQ_DDR_OUT_SLEW_POS 26 /* Slew rate positive for DDR address/clock outputs */
#define CONFIG_EZYNQ_DDR_OUT_DRIVE_NEG 12 /* Drive strength negative for DDR address/clock outputs */
#define CONFIG_EZYNQ_DDR_OUT_DRIVE_POS 28 /* Drive strength positive for DDR address/clock outputs */
#define CONFIG_EZYNQ_DDR_BIDIR_SLEW_NEG 31 /* Slew rate negative for driving DDR DQ/DQS signals */
#define CONFIG_EZYNQ_DDR_BIDIR_SLEW_POS 6 /* Drive strength positive for driving DDR DQ/DQS signals */
#define CONFIG_EZYNQ_DDR_BIDIR_DRIVE_NEG 12 /* Drive strength negative for driving DDR DQ/DQS signals */
#define CONFIG_EZYNQ_DDR_BIDIR_DRIVE_POS 28 /* Slew rate positive for driving DDR DQ/DQS signals */
/* Main clock settings */
#define CONFIG_EZYNQ_CLK_PS_MHZ 33.333333 /* PS_CLK System clock input frequency (MHz) */
#define CONFIG_EZYNQ_CLK_DDR_MHZ 533.333333 /* DDR clock frequency - DDR_3X (MHz) */
#define CONFIG_EZYNQ_CLK_ARM_MHZ 667 /* ARM CPU clock frequency cpu_6x4x (MHz) */
#define CONFIG_EZYNQ_CLK_CPU_MODE 6_2_1 /* CPU clocks set 6:2:1 (6:3:2:1) or 4:2:1 (4:2:2:1) */
#define CONFIG_EZYNQ_CLK_FPGA0_MHZ 50.0 /* FPGA 0 clock frequency (MHz) */
#define CONFIG_EZYNQ_CLK_FPGA1_MHZ 50.0 /* FPGA 1 clock frequency (MHz) */
#define CONFIG_EZYNQ_CLK_FPGA2_MHZ 50.0 /* FPGA 2 clock frequency (MHz) */
#define CONFIG_EZYNQ_CLK_FPGA3_MHZ 0.0 /* FPGA 3 clock frequency (MHz) */
#define CONFIG_EZYNQ_CLK_FPGA0_SRC IO /* FPGA 0 clock source */
#define CONFIG_EZYNQ_CLK_FPGA1_SRC IO /* FPGA 1 clock source */
#define CONFIG_EZYNQ_CLK_FPGA2_SRC None /* FPGA 2 clock source */
#define CONFIG_EZYNQ_CLK_FPGA3_SRC IO /* FPGA 3 clock source */
/* Normally do not need to be modified */
#define CONFIG_EZYNQ_CLK_DDR_DCI_MHZ 10.0 /* DDR DCI clock frequency (MHz). Normally 10 Mhz */
#define CONFIG_EZYNQ_CLK_DDR2X_MHZ 355.556 /* DDR2X clock frequency (MHz). Does not need to be exactly 2/3 of DDR3X clock */
#define CONFIG_EZYNQ_CLK_DDR_DCI_MHZ 10.0 /* DDR DCI clock frequency (MHz). Normally 10Mhz */
#define CONFIG_EZYNQ_CLK_SMC_MHZ 100.0 /* Static memory controller clock frequency (MHz). Normally 100 Mhz */
#define CONFIG_EZYNQ_CLK_QSPI_MHZ 200.0 /* Quad SPI memory controller clock frequency (MHz). Normally 200 Mhz */
#define CONFIG_EZYNQ_CLK_GIGE0_MHZ 125.0 /* GigE 0 Ethernet controller reference clock frequency (MHz). Normally 125 Mhz */
#define CONFIG_EZYNQ_CLK_GIGE1_MHZ 125.0 /* GigE 1 Ethernet controller reference clock frequency (MHz). Normally 125 Mhz */
#define CONFIG_EZYNQ_CLK_SDIO_MHZ 100.0 /* SDIO controller reference clock frequency (MHz). Normally 100 Mhz */
#define CONFIG_EZYNQ_CLK_UART_MHZ 25.0 /* UART controller reference clock frequency (MHz). Normally 25 Mhz */
#define CONFIG_EZYNQ_CLK_SPI_MHZ 200.0 /* SPI controller reference clock frequency (MHz). Normally 200 Mhz */
#define CONFIG_EZYNQ_CLK_CAN_MHZ 100.0 /* CAN controller reference clock frequency (MHz). Normally 100 Mhz */
#define CONFIG_EZYNQ_CLK_PCAP_MHZ 200.0 /* PCAP clock frequency (MHz). Normally 200 Mhz */
#define CONFIG_EZYNQ_CLK_TRACE_MHZ 100.0 /* Trace Port clock frequency (MHz). Normally 100 Mhz */
#define CONFIG_EZYNQ_CLK_ARM_SRC ARM /* ARM CPU clock source (normally ARM PLL) */
#define CONFIG_EZYNQ_CLK_DDR_SRC DDR /* DDR (DDR2x, DDR3x) clock source (normally DDR PLL) */
#define CONFIG_EZYNQ_CLK_DDR_DCI_SRC DDR /* DDR DCI clock source (normally DDR PLL) */
#define CONFIG_EZYNQ_CLK_SMC_SRC IO /* Static memory controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_QSPI_SRC ARM /* Quad SPI memory controller clock source (normally ARM PLL) */
#define CONFIG_EZYNQ_CLK_GIGE0_SRC IO /* GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO) */
#define CONFIG_EZYNQ_CLK_GIGE1_SRC IO /* GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO) */
#define CONFIG_EZYNQ_CLK_SDIO_SRC IO /* SDIO controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_UART_SRC IO /* UART controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_SPI_SRC IO /* SPI controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_CAN_SRC IO /* CAN controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_PCAP_SRC IO /* PCAP controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_TRACE_SRC IO /* Trace Port clock source (normally IO PLL) */
/* Even if memory itself is DDR3L (1.35V) it also can support DDR3 mode (1.5V). And unfortunately Zynq has degraded
specs at 1.35V (only 400MHz maximal clock), so datasheets's 'DDR3L' should be replaced with 'DDR3' and the board
power supply should be 1.5V - in that case 533MHz clock is possible */
#undef CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE
#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE DDR3 /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
/* performance data, final values (overwrite calculated) */
#define CONFIG_EZYNQ_CLK_SPEED_GRADE 3 /* Device speed grade */
/* #define CONFIG_EZYNQ_CLK_PLL_MAX_MHZ 1800.0 */ /* Maximal PLL clock frequency, MHz. Overwrites default for selected speed grade: (Speed grade -1:1600, -2:1800, -3:2000) */
/* #define CONFIG_EZYNQ_CLK_PLL_MIN_MHZ 780.0 */ /* Minimal PLL clock frequency, all speed grades (MHz) */
/* #define CONFIG_EZYNQ_CLK_ARM621_MAX_MHZ 733.0 */ /* Maximal ARM clk_6x4x in 621 mode, MHz. Overwrites default for selected speed grade: (Speed grade -1:667, -2:733, -3:1000) */
/* #define CONFIG_EZYNQ_CLK_ARM421_MAX_MHZ 600.0 */ /* Maximal ARM clk_6x4x in 421 mode, MHz. Overwrites default for selected speed grade: (Speed grade -1:533, -2:600, -3:710) */
/* #define CONFIG_EZYNQ_CLK_DDR_3X_MAX_MHZ 533.0 */ /* Maximal DDR clk_3x clock frequency (MHz). Overwrites DDR-type/speed grade specific */
/* #define CONFIG_EZYNQ_CLK_DDR_2X_MAX_MHZ 408.0 */ /* Maximal DDR_2X clock frequency (MHz). Overwrites speed grade specific */
#define CONFIG_EZYNQ_CLK_COMPLIANCE_PERCENT 5.0 /* Allow exceeding maximal limits by this margin (percent */
/* Board PCB layout parameters (not yet used) */
#define CONFIG_EZYNQ_DDR_BOARD_DELAY0 0.0
#define CONFIG_EZYNQ_DDR_BOARD_DELAY1 0.0
#define CONFIG_EZYNQ_DDR_BOARD_DELAY2 0.0
#define CONFIG_EZYNQ_DDR_BOARD_DELAY3 0.0
#define CONFIG_EZYNQ_DDR_DQS_0_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQS_1_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQS_2_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQS_3_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQ_0_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQ_1_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQ_2_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQ_3_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_CLOCK_0_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_CLOCK_1_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_CLOCK_2_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_CLOCK_3_LENGTH_MM 0
/* Below will overwrite calculated values (not yet calculated) */
#if 1 /*testing old version */
/* LED will be ON */
#define CONFIG_EZYNQ_MIO_INOUT_53 OUT /* Make output, do not set data. Will be set after debug will be over */
#define CONFIG_EZYNQ_MIO_GPIO_OUT_53 0 /* Set selected GPIO output to 0/1 */
#undef CONFIG_EZYNQ_DDR_DS_CKE
#define CONFIG_EZYNQ_DDR_DS_CKE 4 /* CKE min pulse width (in tCK) */
// #undef CONFIG_EZYNQ_DDR_DS_WLMRD
// #define CONFIG_EZYNQ_DDR_DS_WLMRD 22 /* Write leveling : time to the first DQS rising edge (cycles). */
#define CONFIG_EZYNQ_LED_DEBUG 53 /* toggle LED during boot - temporary, normal use - MDIO_D */
#define CONFIG_EZYNQ_UART_DEBUG_USE_LED /* turn on/off LED while waiting for transmit FIFO not full */
#define CONFIG_EZYNQ_SILICON 3 /* 3 */ /* Silicon revision */
#define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_0 0x0 /* Initial ratio for write leveling FSM, slice 0 */
#define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_1 0x0 /* Initial ratio for write leveling FSM, slice 1 */
#define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_2 0x0 /* Initial ratio for write leveling FSM, slice 2 */
#define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_3 0x0 /* Initial ratio for write leveling FSM, slice 3 */
#define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_0 0x0 /* Initial ratio for gate leveling FSM, slice 0 */
#define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_1 0x0 /* Initial ratio for gate leveling FSM, slice 1 */
#define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_2 0x0 /* Initial ratio for gate leveling FSM, slice 2 */
#define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_3 0x0 /* Initial ratio for gate leveling FSM, slice 3 */
#define CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_0 0x35/* Ratio for read DQS slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_1 0x35/* Ratio for read DQS slave DLL (256 - clock period), slice 1 */
#define CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_2 0x35/* Ratio for read DQS slave DLL (256 - clock period), slice 2 */
#define CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_3 0x35/* Ratio for read DQS slave DLL (256 - clock period), slice 3 */
#define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_0 0x0 /* Ratio for write DQS slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_1 0x0 /* Ratio for write DQS slave DLL (256 - clock period), slice 1 */
#define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_2 0x0 /* Ratio for write DQS slave DLL (256 - clock period), slice 2 */
#define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_3 0x0 /* Ratio for write DQS slave DLL (256 - clock period), slice 3 */
#define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_0 0x35 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_1 0x35 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_2 0x35 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_3 0x35 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_0 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_1 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 1 */
#define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_2 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 2 */
#define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_3 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 3 */
#define CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO 0x80 /* Ratio for address/command (256 - clock period) */
#define CONFIG_EZYNQ_PHY_INVERT_CLK N /* RInvert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
#else
#define CONFIG_EZYNQ_MIO_ETH_MDIO__SLOW
#define CONFIG_EZYNQ_SILICON 3 /* 3 */ /* Silicon revision */
#define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_0 0x4 /* Initial ratio for write leveling FSM, slice 0 */
#define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_1 0x0 /* Initial ratio for write leveling FSM, slice 1 */
#define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_2 0x5 /* Initial ratio for write leveling FSM, slice 2 */
#define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_3 0x7 /* Initial ratio for write leveling FSM, slice 3 */
#define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_0 0x8e /* Initial ratio for gate leveling FSM, slice 0 */
#define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_1 0x95 /* Initial ratio for gate leveling FSM, slice 1 */
#define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_2 0x8e /* Initial ratio for gate leveling FSM, slice 2 */
#define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_3 0x8c /* Initial ratio for gate leveling FSM, slice 3 */
#define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_0 0x84 /* Ratio for write DQS slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_1 0x80 /* Ratio for write DQS slave DLL (256 - clock period), slice 1 */
#define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_2 0x85 /* Ratio for write DQS slave DLL (256 - clock period), slice 2 */
#define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_3 0x87 /* Ratio for write DQS slave DLL (256 - clock period), slice 3 */
#define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_0 0xe3 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_1 0xea /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_2 0xe3 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_3 0xe1 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_0 0xc4 /* Ratio for write data slave DLL (256 - clock period), slice 0 */
#define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_1 0xc0 /* Ratio for write data slave DLL (256 - clock period), slice 1 */
#define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_2 0xc5 /* Ratio for write data slave DLL (256 - clock period), slice 2 */
#define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_3 0xc7 /* Ratio for write data slave DLL (256 - clock period), slice 3 */
#define CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO 0x100 /* Ratio for address/command (256 - clock period) */
#define CONFIG_EZYNQ_PHY_INVERT_CLK /* RInvert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
#endif
/* not yet processed
#define CONFIG_EZYNQ_DDR_PERIPHERAL_CLKSRC DDR PLL
#define CONFIG_EZYNQ_DDR_RAM_BASEADDR 0x00100000
#define CONFIG_EZYNQ_DDR_RAM_HIGHADDR 0x3FFFFFFF
*/
#endif /* __CONFIG_EZYNQ_H */
u-boot-tree/include/configs/ezynq/ezynq_MT41K256M16HA107.h 0 → 100644
View file @ 435a11b3
/*
* (C) Copyright 2013 Elphel, Inc.
*
* Configuration for ezynq for Micron MT41K256M16HA107 DDR3L memory
* backward compatible to Micron MT41K256M16RE125 (used in microzed, will keep settings initially)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_EZYNQ_MT41K256M16RE125_H
#define __CONFIG_EZYNQ_MT41K256M16RE125_H
#define CONFIG_EZYNQ_DDR_DS_PARTNO MT41K256M16HA107 /* Memory part number (currently not used - derive some parameters later) */
/* CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE will be redefined to DDR3 as Zynq is slow with DDR3 */
#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE DDR3L /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
#define CONFIG_EZYNQ_DDR_DS_BANK_ADDR_COUNT 3 /* Number of DDR banks */
#define CONFIG_EZYNQ_DDR_DS_ROW_ADDR_COUNT 15 /* Number of DDR Row Address bits */
#define CONFIG_EZYNQ_DDR_DS_COL_ADDR_COUNT 10 /* Number of DDR Column address bits */
#define CONFIG_EZYNQ_DDR_DS_DRAM_WIDTH 16 /* Memory chip bus width (not yet used) */
#define CONFIG_EZYNQ_DDR_DS_RCD 7 /* DESCRIPTION':'RAS to CAS delay (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_RCD 13.1 /* Activate to internal Read or Write (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RCD automatically */
#define CONFIG_EZYNQ_DDR_DS_RP 7 /* Row Precharge time (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_RP 13.1 /* Precharge command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RP automatically, */
#define CONFIG_EZYNQ_DDR_DS_T_RC 48.75/* Activate to Activate or Refresh command period (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_RAS_MIN 35.0 /* Minimal Row Active time (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_FAW 40.0 /* Minimal running window for 4 page activates (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_RFC 300.0 /* Minimal Refresh-to-Activate or Refresh command period (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_WR 15.0 /* Write recovery time (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_REFI_US 7.8 /* Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected */
#define CONFIG_EZYNQ_DDR_DS_RTP 4 /* Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK */
#define CONFIG_EZYNQ_DDR_DS_T_RTP 7.5 /* Minimal Read-to-Precharge time (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP */
#define CONFIG_EZYNQ_DDR_DS_WTR 4 /* Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK */
#define CONFIG_EZYNQ_DDR_DS_T_WTR 7.5 /* Minimal Write-to-Read time (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR */
#define CONFIG_EZYNQ_DDR_DS_XP 4 /* Minimal time from power down (DLL on) to any operation (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX 5.5 /* LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2 */
#define CONFIG_EZYNQ_DDR_DS_CCD 5 /* DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS) */
#define CONFIG_EZYNQ_DDR_DS_RRD 6 /* ACTIVATE-to-ACTIVATE minimal command period (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_RRD 10.0 /* ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically */
#define CONFIG_EZYNQ_DDR_DS_MRD 4 /* MODE REGISTER SET command period (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_MOD 12 /* MODE REGISTER SET update delay (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_MOD 15.0 /* MODE REGISTER SET update delay (ns). */
#define CONFIG_EZYNQ_DDR_DS_WLMRD 40 /* Write leveling : time to the first DQS rising edge (cycles). */
#define CONFIG_EZYNQ_DDR_DS_CKE 3 /* CKE min pulse width (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_CKE 5.625 /* CKE min pulse width (ns). 7.5 */
#define CONFIG_EZYNQ_DDR_DS_CKSRE 5 /* Keep valid clock after self refresh/power down entry (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_CKSRE 10.0 /* Keep valid clock after self refresh/power down entry (ns). */
#define CONFIG_EZYNQ_DDR_DS_CKSRX 5 /* Valid clock before self refresh, power down or reset exit (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_CKSRX 10.0 /* Valid clock before self refresh, power down or reset exit (ns). */
#define CONFIG_EZYNQ_DDR_DS_ZQCS 64 /* ZQCS command: short calibration time (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_ZQCL 512 /* ZQCL command: long calibration time, including init (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_INIT2 5 /* LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high */
#define CONFIG_EZYNQ_DDR_DS_T_INIT4_US 1.0 /* LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET command. */
#define CONFIG_EZYNQ_DDR_DS_T_INIT5_US 10.0 /* LPDDR2 only: tINIT5 (in us)- maximal duration of device auto initialization. */
#define CONFIG_EZYNQ_DDR_DS_T_ZQINIT_US 1.0 /* LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time. */
#endif /* __CONFIG_EZYNQ_MT41K256M16RE125_H */
u-boot-tree/include/configs/ezynq/ezynq_MT41K256M16RE125.h
View file @ 435a11b3
......@@ -46,9 +46,9 @@
#define CONFIG_EZYNQ_DDR_DS_MRD 4 /* MODE REGISTER SET command period (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_MOD 12 /* MODE REGISTER SET update delay (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_MOD 15.0 /* MODE REGISTER SET update delay (ns). */
#define CONFIG_EZYNQ_DDR_DS_T_WLMRD 40.0 /* Write leveling : time to the first DQS rising edge (ns). */
#define CONFIG_EZYNQ_DDR_DS_WLMRD 40 /* Write leveling : time to the first DQS rising edge (cycles). */
#define CONFIG_EZYNQ_DDR_DS_CKE 3 /* CKE min pulse width (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_CKE 7.5 /* CKE min pulse width (ns). 5.625 */
#define CONFIG_EZYNQ_DDR_DS_T_CKE 5.625 /* CKE min pulse width (ns). 7.5 */
#define CONFIG_EZYNQ_DDR_DS_CKSRE 5 /* Keep valid clock after self refresh/power down entry (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_CKSRE 10.0 /* Keep valid clock after self refresh/power down entry (ns). */
#define CONFIG_EZYNQ_DDR_DS_CKSRX 5 /* Valid clock before self refresh, power down or reset exit (in tCK) */
......
u-boot-tree/include/configs/ezynq/ezynq_XC7Z030_1FBG484C.h 0 → 100644
View file @ 435a11b3
/*
* (C) Copyright 2013 Elphel, Inc.
*
* Configuration for ezynq for Xilinx XC7Z030_1FBG484C SoC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_XC7Z010_1CLG400_H
#define __CONFIG_XC7Z010_1CLG400_H
/* datasheet data for specific speed grades */
#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ 1600.0 /* Maximal PLL clock frequency for speed grade 1 (MHz) */
#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ 1800.0 /* Maximal PLL clock frequency for speed grade 2 (MHz) */
#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ 2000.0 /* Maximal PLL clock frequency for speed grade 3 (MHz) */
#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ 667.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ 800.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ 1000.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ 533.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ 600.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ 710.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz */
#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS 1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS 1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS 1333.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
#define CONFIG_EZYNQ_CLK_DS_DDR3L_MAX_1_MBPS 1066.0 /* Maximal DDR3L performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
#define CONFIG_EZYNQ_CLK_DS_DDR3L_MAX_2_MBPS 1066.0 /* Maximal DDR3L performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
#define CONFIG_EZYNQ_CLK_DS_DDR3L_MAX_3_MBPS 1066.0 /* Maximal DDR3L performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
#define CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS 800.0 /* Maximal DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades */
#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ 355.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 1 */
#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ 408.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 2 */
#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ 444.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 3 */
/* SoC parameters to set phases manually (or as a starting point for automatic) Not yet processed */
/* TODO: not yet modified from XC7Z010_1CLG400 */
#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0 0.0
#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1 0.0
#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2 0.0
#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3 0.0
#define CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH 504
#define CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH 495
#define CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH 520
#define CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH 835
#define CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH 465
#define CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH 480
#define CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH 550
#define CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH 780
#define CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH 470.0
#define CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH 470.0
#define CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH 470.0
#define CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH 470.0
/* Sorry for propOgation - this is how it is called in the tools */
#define CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY 160
#endif /* __CONFIG_XC7Z010_1CLG400_H */
u-boot-tree/include/configs/ezynq/zed_ezynq.h
View file @ 435a11b3
......@@ -68,7 +68,7 @@
#define CONFIG_EZYNQ_MIO_UART_1 48 /* # 8+4*N */
/* LED will be OFF */
#define CONFIG_EZYNQ_MIO_INOUT_47 OUT /* Make output, do not set data. Will be set after debug will be over */
#define CONFIG_EZYNQ_MIO_GPIO_OUT_7= 1 /* Set selected GPIO output to 0/1 */
#define CONFIG_EZYNQ_MIO_GPIO_OUT_7 1 /* Set selected GPIO output to 0/1 */
/*
Red LED - pullup, input - on,
......
u-boot-tree/include/configs/ezynq/zynq_microzed.h 0 → 100644
View file @ 435a11b3
/*
* (C) Copyright 2012 Xilinx
*
* Configuration for Zynq Evaluation and Development Board - ZedBoard
* See zynq_common.h for Zynq common configs
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_ZYNQ_MICROZED_H
#define __CONFIG_ZYNQ_MICROZED_H
/*#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) */
#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
#if 0
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#endif
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0
//#define CONFIG_ZYNQ_SPI
//#define CONFIG_NAND_ZYNQ
#undef CONFIG_SYS_TEXT_BASE
#include <configs/zynq_common.h>
#include <configs/ezynq/ezynq_MT41K256M16RE125.h> /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
#include <configs/ezynq/ezynq_XC7Z010_1CLG400.h>
#include <configs/ezynq/zed_ezynq.h>
//#define CONFIG_CMD_MEMTEST
#undef CONFIG_EZYNQ_BOOT_DEBUG
/* twice slower */
#undef CONFIG_ZYNQ_SERIAL_CLOCK0
/*#define CONFIG_ZYNQ_SERIAL_CLOCK0 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK0 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_ZYNQ_SERIAL_CLOCK1
/*#define CONFIG_ZYNQ_SERIAL_CLOCK1 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK1 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_BOOTDELAY
#undef CONFIG_SYS_PROMPT
#undef CONFIG_SYS_SDRAM_BASE
#undef CONFIG_ENV_SIZE
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_BOOTDELAY -1 /* -1 to Disable autoboot */
#define CONFIG_SYS_PROMPT "ezynq> "
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Physical start address of SDRAM. _Must_ be 0 here. */
#define CONFIG_ENV_SIZE 1400
#if 0
#define CONFIG_SYS_TEXT_BASE 0x04000000 /*with 0x04000000 - does not get to the low_Level_init? */
#else
#define CONFIG_SYS_TEXT_BASE 0x00000000 //0x04000000 with 0x04000000 - does not get to the low_Level_init?
#endif
/*
#define CONFIG_EZYNQ_SKIP_DDR
*/
#define CONFIG_EZYNQ_SKIP_CLK
//undefs
/* undefs */
/*#undef CONFIG_FS_FAT */
/* #undef CONFIG_SUPPORT_VFAT */
/* #undef CONFIG_CMD_FAT */
/* http://lists.denx.de/pipermail/u-boot/2003-October/002631.html */
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
/* CONFIG_FS_FAT=y */
/* disable PL*/
#undef CONFIG_FPGA
#undef CONFIG_FPGA_XILINX
#undef CONFIG_FPGA_ZYNQPL
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_EXT2
#undef CONFIG_CMD_CACHE
#undef DEBUG
#undef CONFIG_AUTO_COMPLETE
#undef CONFIG_SYS_LONGHELP
/* redefine env settings*/
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ethaddr=00:0a:35:00:01:22\0" \
"kernel_image=uImage\0" \
"ramdisk_image=uramdisk.image.gz\0" \
"devicetree_image=devicetree.dtb\0" \
"bitstream_image=system.bit.bin\0" \
"loadbit_addr=0x100000\0" \
"kernel_size=0x500000\0" \
"devicetree_size=0x20000\0" \
"ramdisk_size=0x5E0000\0" \
"fdt_high=0x20000000\0" \
"initrd_high=0x20000000\0" \
"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
"mmcinfo && " \
"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
"fpga load 0 ${loadbit_addr} ${filesize}\0" \
"sdboot=echo Copying Linux from SD to RAM... && " \
"mmcinfo && " \
"fatload mmc 0 0x3000000 ${kernel_image} && " \
"fatload mmc 0 0x2A00000 ${devicetree_image} && " \
"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"nandboot=echo Copying Linux from NAND flash to RAM... && " \
"nand read 0x3000000 0x100000 ${kernel_size} && " \
"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
"echo Copying ramdisk... && " \
"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0"
/* */
#endif /* __CONFIG_ZYNQ_MICROZED_H */
u-boot-tree/makeuboot393 0 → 100755
View file @ 435a11b3
#!/bin/bash
. ./initenv
make clean
make elphel393_config
make include/autoconf.mk
echo "Running ezynqcfg.py for the first time - u-boot.bin length is not known yet, generating arch/arm/cpu/armv7/zynq/ezynq.c"
ezynq/ezynqcfg.py -c include/autoconf.mk --html u-boot.html -o boot_head.bin --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/ezynq.c
make
echo "Running ezynqcfg.py for the second time - u-boot.bin length is known and will be used in the RBL header"
echo "Other files are already created, repeating it here just to remind their paths"
ezynq/ezynqcfg.py -c include/autoconf.mk -o boot_head.bin --uboot u-boot.bin --html u-boot.html --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/ezynq.c
cat boot_head.bin u-boot.bin > boot.bin
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