Commit 33bcc7d2 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
Browse files

1. zedboard ezynq pre-test config

parent 24e5f615

README.md

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@@ -70,6 +70,7 @@ OCM limit is not in effect anymore. 
* **Avnet MicroZed**

* **Xilinx ZC706**

* **Elphel 10393**

* **Digilent/Avnet Zedboard** (not yet tested)



## INSTALLATION (see below for testing without U-boot installation)
@@ -87,7 +88,7 @@ These links created by install_uboot.sh add new configuration files and replace 
* arch/arm/cpu/armv7/zynq/Makefile - to add autogenerated (not in the repository)

  arch/arm/cpu/armv7/zynq/ezynq.c



New files include:

New files include (for microzed):



* *include/configs/zynq_microzed.h* configuration parameters for U-boot features, described in

  U-boot README file
@@ -95,9 +96,7 @@ New files include: 
  Micron DDR3 memory datasheet for the memory used by MicroZed board

* *include/configs/ezynq/ezynq_XC7Z010_1CLG400.h* - Ezynq configuration parameters containing

  Xilinx Zynq datasheet data for the SoC used by MicroZed board

* *include/configs/ezynq/ezynq_XC7Z010_1CLG400.h* - Ezynq configuration parameters containing

  Xilinx Zynq datasheet data for the SoC used by MicroZed board

* include/configs/ezynq/zed_ezynq.h - rest of the Ezynq configuration parameters (it has the

* include/configs/ezynq/ezynq_microzed.h - rest of the Ezynq configuration parameters (it has the

  include lines for the 2 datasheet files listed above)

* *makeuboot* - script that configures U-boot for the microzed board, creates include/autoconf.mk,

  runs ezynqcfg.py to create Ezynq code (RBL header and ezynq.c), builds and links U-boot

u-boot-tree/include/configs/ezynq/ezynq_MT41J128M16HA15E.h

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 /*

 * (C) Copyright 2013 Elphel, Inc.

 *

 * Configuration for ezynq for Micron MT41K256M16HA107 DDR3L memory

 * backward compatible to Micron MT41K256M16RE125 (used in microzed, will keep settings initially)

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 3 of

 * the License, or (at your option) any later version.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 */

#ifndef __CONFIG_EZYNQ_MT41J128M16HA15E_H

#define __CONFIG_EZYNQ_MT41J128M16HA15E_H



#define CONFIG_EZYNQ_DDR_DS_PARTNO           MT41J128M16HA15E /* Memory part number  (currently not used - derive some parameters later) */

/* CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE will be redefined to DDR3 as Zynq is slow with DDR3 */

#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE      DDR3  /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */



#define CONFIG_EZYNQ_DDR_DS_BANK_ADDR_COUNT   3  /* Number of DDR banks */

#define CONFIG_EZYNQ_DDR_DS_ROW_ADDR_COUNT   15  /* Number of DDR Row Address bits */

#define CONFIG_EZYNQ_DDR_DS_COL_ADDR_COUNT   10  /* Number of DDR Column address bits */

#define CONFIG_EZYNQ_DDR_DS_DRAM_WIDTH       16  /* Memory chip bus width (not yet used) */

#define CONFIG_EZYNQ_DDR_DS_RCD              7   /* DESCRIPTION':'RAS to CAS delay (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_T_RCD           13.1 /* Activate to internal Read or Write (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RCD automatically */

#define CONFIG_EZYNQ_DDR_DS_RP               7   /* Row Precharge time (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_T_RP             13.1 /* Precharge command period (ns).  May be used to calculate CONFIG_EZYNQ_DDR_DS_RP automatically, */

#define CONFIG_EZYNQ_DDR_DS_T_RC             48.75/* Activate to Activate or Refresh command period (ns) */

#define CONFIG_EZYNQ_DDR_DS_T_RAS_MIN        35.0 /* Minimal Row Active time (ns) */

#define CONFIG_EZYNQ_DDR_DS_T_FAW            40.0 /* Minimal running window for 4 page activates (ns) */

#define CONFIG_EZYNQ_DDR_DS_T_RFC           300.0 /* Minimal Refresh-to-Activate or Refresh command period (ns) */

#define CONFIG_EZYNQ_DDR_DS_T_WR             15.0 /* Write recovery time (ns) */

#define CONFIG_EZYNQ_DDR_DS_T_REFI_US         7.8 /* Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected */

#define CONFIG_EZYNQ_DDR_DS_RTP               4 /* Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK */

#define CONFIG_EZYNQ_DDR_DS_T_RTP             7.5 /* Minimal Read-to-Precharge time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP */

#define CONFIG_EZYNQ_DDR_DS_WTR               4   /* Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK */

#define CONFIG_EZYNQ_DDR_DS_T_WTR             7.5 /* Minimal Write-to-Read time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR */

#define CONFIG_EZYNQ_DDR_DS_XP                4   /* Minimal time from power down (DLL on) to any operation (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX       5.5 /* LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2 */

#define CONFIG_EZYNQ_DDR_DS_CCD               5   /* DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS) */

#define CONFIG_EZYNQ_DDR_DS_RRD               6   /* ACTIVATE-to-ACTIVATE minimal command period (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_T_RRD            10.0 /* ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically */

#define CONFIG_EZYNQ_DDR_DS_MRD               4   /* MODE REGISTER SET command period (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_MOD              12   /* MODE REGISTER SET update delay (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_T_MOD            15.0 /* MODE REGISTER SET update delay  (ns). */

#define CONFIG_EZYNQ_DDR_DS_WLMRD            40   /* Write leveling : time to the first DQS rising edge (cycles). */

#define CONFIG_EZYNQ_DDR_DS_CKE               3   /* CKE min pulse width (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_T_CKE             7.5 /* CKE min pulse width (ns). 7.5  */

#define CONFIG_EZYNQ_DDR_DS_CKSRE             5   /* Keep valid clock after self refresh/power down entry (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_T_CKSRE          10.0 /* Keep valid clock after self refresh/power down entry (ns). */

#define CONFIG_EZYNQ_DDR_DS_CKSRX             5   /* Valid clock before self refresh, power down or reset exit (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_T_CKSRX          10.0 /* Valid clock before self refresh, power down or reset exit (ns). */

#define CONFIG_EZYNQ_DDR_DS_ZQCS             64   /* ZQCS command: short calibration time (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_ZQCL            512   /* ZQCL command: long calibration time, including init (in tCK) */

#define CONFIG_EZYNQ_DDR_DS_INIT2             5   /* LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high */

#define CONFIG_EZYNQ_DDR_DS_T_INIT4_US        1.0 /* LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET command. */

#define CONFIG_EZYNQ_DDR_DS_T_INIT5_US       10.0 /* LPDDR2 only: tINIT5 (in us)- maximal duration of device auto initialization. */

#define CONFIG_EZYNQ_DDR_DS_T_ZQINIT_US       1.0 /* LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time. */





#endif /* __CONFIG_EZYNQ_MT41J128M16HA15E_H */

u-boot-tree/include/configs/ezynq/ezynq_XC7Z020_1CLG484.h

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 /*

 * (C) Copyright 2013 Elphel, Inc.

 *

 * Configuration for ezynq for Xilinx XC7Z020_1CLG484 SoC

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 3 of

 * the License, or (at your option) any later version.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 */

#ifndef __CONFIG_XC7Z020_1CLG484_H

#define __CONFIG_XC7Z020_1CLG484_H



/* datasheet data for specific speed grades */

#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ     1600.0 /* Maximal PLL clock frequency for speed grade 1 (MHz) */

#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ     1800.0 /* Maximal PLL clock frequency for speed grade 2 (MHz) */

#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ     2000.0 /* Maximal PLL clock frequency for speed grade 3 (MHz) */

#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ   667.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz */

#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ   733.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz */

#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ  1000.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz */

#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ   533.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz */

#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ   600.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz */

#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ   710.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz */

#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */

#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */

#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS   1333.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */

#define CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS    800.0 /* Maximal DDR3L, DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades */

#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ   355.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 1 */

#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ   408.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 2 */

#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ   444.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 3 */



/*  SoC  parameters to set phases manually (or as a starting point for automatic) Not yet processed */

#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0        0.0

#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1        0.0

#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2        0.0

#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3        0.0

#define CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH      504

#define CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH      495

#define CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH      520

#define CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH      835

#define CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH       465

#define CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH       480

#define CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH       550

#define CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH       780

#define CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH    470.0

#define CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH    470.0

#define CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH    470.0

#define CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH    470.0

/* Sorry for propOgation - this is how it is called in the tools */

#define CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY   160

#define CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY   160

#define CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY   160

#define CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY   160

#define CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY    160

#define CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY    160

#define CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY    160

#define CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY    160

#define CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY 160

#define CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY 160

#define CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY 160

#define CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY 160





#endif /* __CONFIG_XC7Z020_1CLG484_H */

u-boot-tree/include/configs/ezynq/ezynq_zed.h

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u-boot-tree/include/configs/zynq_zed.h

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/*

 * (C) Copyright 2012 Xilinx

 *

 * Configuration for Zynq Evaluation and Development Board - ZedBoard

 * See zynq_common.h for Zynq common configs

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 of

 * the License, or (at your option) any later version.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 */



#ifndef __CONFIG_ZYNQ_ZED_H

#define __CONFIG_ZYNQ_ZED_H



#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) 



#define CONFIG_ZYNQ_SERIAL_UART1

#if 0

#define CONFIG_ZYNQ_GEM0

#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0

#endif



#define CONFIG_SYS_NO_FLASH



#define CONFIG_ZYNQ_SDHCI0

/* #define CONFIG_ZYNQ_SPI */



/* #define CONFIG_NAND_ZYNQ */

#undef CONFIG_SYS_TEXT_BASE

#include <configs/zynq_common.h>

#include <configs/ezynq/ezynq_MT41J128M16HA15E.h>  /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */

#include <configs/ezynq/ezynq_XC7Z020_1CLG484.h>

#include <configs/ezynq/ezynq_zed.h>



#if 0

  #undef CONFIG_EZYNQ_BOOT_DEBUG            /* configure UARTx and send register dumps there.*/

#endif

#define CONFIG_CMD_MEMTEST



/* twice slower */

#undef CONFIG_ZYNQ_SERIAL_CLOCK0

/*#define CONFIG_ZYNQ_SERIAL_CLOCK0	25000000*/

#define CONFIG_ZYNQ_SERIAL_CLOCK0	1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)

#undef CONFIG_ZYNQ_SERIAL_CLOCK1

/*#define CONFIG_ZYNQ_SERIAL_CLOCK1	25000000*/

#define CONFIG_ZYNQ_SERIAL_CLOCK1	1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)





#undef CONFIG_BOOTDELAY

#undef CONFIG_SYS_PROMPT

#undef CONFIG_SYS_SDRAM_BASE

#undef CONFIG_ENV_SIZE

#undef CONFIG_SYS_TEXT_BASE



#define CONFIG_BOOTDELAY	-1 /* -1 to Disable autoboot */

#define CONFIG_SYS_PROMPT		"ezynq> "





#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* Physical start address of SDRAM. _Must_ be 0 here. */

#define CONFIG_ENV_SIZE		        1400

#if 0

  #define CONFIG_SYS_TEXT_BASE		0x04000000 /*with 0x04000000 - does not get to the low_Level_init? */

#else

#define CONFIG_SYS_TEXT_BASE		0x00000000

#endif

/*

#define CONFIG_EZYNQ_SKIP_DDR

*/

#define CONFIG_EZYNQ_SKIP_CLK



/* undefs */



/* undefs */

/*#undef CONFIG_FS_FAT */

/* #undef CONFIG_SUPPORT_VFAT */

/* #undef CONFIG_CMD_FAT */

/* http://lists.denx.de/pipermail/u-boot/2003-October/002631.html */

#undef CONFIG_CMD_LOADB

#undef CONFIG_CMD_LOADS

#undef CONFIG_ZLIB

#undef CONFIG_GZIP

/* CONFIG_FS_FAT=y */





/* disable PL*/

#undef CONFIG_FPGA

#undef CONFIG_FPGA_XILINX

#undef CONFIG_FPGA_ZYNQPL

#undef CONFIG_CMD_FPGA



#undef CONFIG_CMD_EXT2



#undef CONFIG_CMD_CACHE



#undef DEBUG

#undef CONFIG_AUTO_COMPLETE

#undef CONFIG_SYS_LONGHELP



/* redefine env settings*/

#undef CONFIG_EXTRA_ENV_SETTINGS

#define CONFIG_EXTRA_ENV_SETTINGS	\

	"ethaddr=00:0a:35:00:01:22\0"	\

	"kernel_image=uImage\0"	\

	"ramdisk_image=uramdisk.image.gz\0"	\

	"devicetree_image=devicetree.dtb\0"	\

	"bitstream_image=system.bit.bin\0"	\

	"loadbit_addr=0x100000\0"	\

	"kernel_size=0x500000\0"	\

	"devicetree_size=0x20000\0"	\

	"ramdisk_size=0x5E0000\0"	\

	"fdt_high=0x20000000\0"	\

	"initrd_high=0x20000000\0"	\

	"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \

		"mmcinfo && " \

		"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \

		"fpga load 0 ${loadbit_addr} ${filesize}\0" \

	"sdboot=echo Copying Linux from SD to RAM... && " \

		"mmcinfo && " \

		"fatload mmc 0 0x3000000 ${kernel_image} && " \

		"fatload mmc 0 0x2A00000 ${devicetree_image} && " \

		"fatload mmc 0 0x2000000 ${ramdisk_image} && " \

		"bootm 0x3000000 0x2000000 0x2A00000\0" \

	"nandboot=echo Copying Linux from NAND flash to RAM... && " \

		"nand read 0x3000000 0x100000 ${kernel_size} && " \

		"nand read 0x2A00000 0x600000 ${devicetree_size} && " \

		"echo Copying ramdisk... && " \

		"nand read 0x2000000 0x620000 ${ramdisk_size} && " \

		"bootm 0x3000000 0x2000000 0x2A00000\0"

/*  */

#endif /* __CONFIG_ZYNQ_ZED_H */