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ezynq
Commit 27df5bb0 authored by Andrey Filippov's avatar Andrey Filippov
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Added GPIO output setup

parent 7fab1300
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ezynq_gpio_defs.py 0 → 100644
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#!/usr/bin/env python
# Copyright (C) 2013, Elphel.inc.
# Definitions of Zynq GPIO registers
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2013, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
# GPIO Registers
GPIO_DEFS={ #not all fields are defined currently
'BASE_ADDR':(0xE000A000,), # GPIO
'MODULE_NAME':('gpio',),
'mask_data_0_lsw': {'OFFS': 0x000,'DFLT':0xffff0000,'RW':'RW','FORCE_DFLT':True,
'COMMENTS':'Maskable Output Data (GPIO MIO[0:15])',
'FIELDS':{
'mask15': {'r':(31,31),'d':1, 'c':'MIO[15]: 1 - keep, 0 - update, reads 0'},
'mask14': {'r':(30,30),'d':1, 'c':'MIO[14]: 1 - keep, 0 - update, reads 0'},
'mask13': {'r':(29,29),'d':1, 'c':'MIO[13]: 1 - keep, 0 - update, reads 0'},
'mask12': {'r':(28,28),'d':1, 'c':'MIO[12]: 1 - keep, 0 - update, reads 0'},
'mask11': {'r':(27,27),'d':1, 'c':'MIO[11]: 1 - keep, 0 - update, reads 0'},
'mask10': {'r':(26,26),'d':1, 'c':'MIO[10]: 1 - keep, 0 - update, reads 0'},
'mask09': {'r':(25,25),'d':1, 'c':'MIO[ 9]: 1 - keep, 0 - update, reads 0'},
'mask08': {'r':(24,24),'d':1, 'c':'MIO[ 8]: 1 - keep, 0 - update, reads 0'},
'mask07': {'r':(23,23),'d':1, 'c':'MIO[ 7]: 1 - keep, 0 - update, reads 0'},
'mask06': {'r':(22,22),'d':1, 'c':'MIO[ 6]: 1 - keep, 0 - update, reads 0'},
'mask05': {'r':(21,21),'d':1, 'c':'MIO[ 5]: 1 - keep, 0 - update, reads 0'},
'mask04': {'r':(20,20),'d':1, 'c':'MIO[ 4]: 1 - keep, 0 - update, reads 0'},
'mask03': {'r':(19,19),'d':1, 'c':'MIO[ 3]: 1 - keep, 0 - update, reads 0'},
'mask02': {'r':(18,18),'d':1, 'c':'MIO[ 2]: 1 - keep, 0 - update, reads 0'},
'mask01': {'r':(17,17),'d':1, 'c':'MIO[ 1]: 1 - keep, 0 - update, reads 0'},
'mask00': {'r':(16,16),'d':1, 'c':'MIO[ 0]: 1 - keep, 0 - update, reads 0'},
'data15': {'r':(15,15),'d':0, 'c':'MIO[15]: data out'},
'data14': {'r':(14,15),'d':0, 'c':'MIO[14]: data out'},
'data13': {'r':(13,15),'d':0, 'c':'MIO[13]: data out'},
'data12': {'r':(12,15),'d':0, 'c':'MIO[12]: data out'},
'data11': {'r':(11,15),'d':0, 'c':'MIO[11]: data out'},
'data10': {'r':(10,10),'d':0, 'c':'MIO[10]: data out'},
'data09': {'r':( 9, 9),'d':0, 'c':'MIO[ 9]: data out'},
'data08': {'r':( 8, 8),'d':0, 'c':'MIO[ 8]: data out'},
'data07': {'r':( 7, 7),'d':0, 'c':'MIO[ 7]: data out'},
'data06': {'r':( 6, 6),'d':0, 'c':'MIO[ 6]: data out'},
'data05': {'r':( 5, 5),'d':0, 'c':'MIO[ 5]: data out'},
'data04': {'r':( 4, 4),'d':0, 'c':'MIO[ 4]: data out'},
'data03': {'r':( 3, 3),'d':0, 'c':'MIO[ 3]: data out'},
'data02': {'r':( 2, 2),'d':0, 'c':'MIO[ 2]: data out'},
'data01': {'r':( 1, 1),'d':0, 'c':'MIO[ 1]: data out'},
'data00': {'r':( 0, 0),'d':0, 'c':'MIO[ 0]: data out'}}},
'mask_data_0_msw': {'OFFS': 0x004,'DFLT':0xffff0000,'RW':'RW','FORCE_DFLT':True,
'COMMENTS':'Maskable Output Data (GPIO MIO[16:31])',
'FIELDS':{
'mask31': {'r':(31,31),'d':1, 'c':'MIO[31]: 1 - keep, 0 - update, reads 0'},
'mask30': {'r':(30,30),'d':1, 'c':'MIO[30]: 1 - keep, 0 - update, reads 0'},
'mask29': {'r':(29,29),'d':1, 'c':'MIO[29]: 1 - keep, 0 - update, reads 0'},
'mask28': {'r':(28,28),'d':1, 'c':'MIO[28]: 1 - keep, 0 - update, reads 0'},
'mask27': {'r':(27,27),'d':1, 'c':'MIO[27]: 1 - keep, 0 - update, reads 0'},
'mask26': {'r':(26,26),'d':1, 'c':'MIO[26]: 1 - keep, 0 - update, reads 0'},
'mask25': {'r':(25,25),'d':1, 'c':'MIO[25]: 1 - keep, 0 - update, reads 0'},
'mask24': {'r':(24,24),'d':1, 'c':'MIO[24]: 1 - keep, 0 - update, reads 0'},
'mask23': {'r':(23,23),'d':1, 'c':'MIO[23]: 1 - keep, 0 - update, reads 0'},
'mask22': {'r':(22,22),'d':1, 'c':'MIO[22]: 1 - keep, 0 - update, reads 0'},
'mask21': {'r':(21,21),'d':1, 'c':'MIO[21]: 1 - keep, 0 - update, reads 0'},
'mask20': {'r':(20,20),'d':1, 'c':'MIO[20]: 1 - keep, 0 - update, reads 0'},
'mask19': {'r':(19,19),'d':1, 'c':'MIO[19]: 1 - keep, 0 - update, reads 0'},
'mask18': {'r':(18,18),'d':1, 'c':'MIO[18]: 1 - keep, 0 - update, reads 0'},
'mask17': {'r':(17,17),'d':1, 'c':'MIO[17]: 1 - keep, 0 - update, reads 0'},
'mask16': {'r':(16,16),'d':1, 'c':'MIO[16]: 1 - keep, 0 - update, reads 0'},
'data31': {'r':(15,15),'d':0, 'c':'MIO[31]: data out'},
'data30': {'r':(14,15),'d':0, 'c':'MIO[30]: data out'},
'data29': {'r':(13,15),'d':0, 'c':'MIO[29]: data out'},
'data28': {'r':(12,15),'d':0, 'c':'MIO[28]: data out'},
'data27': {'r':(11,15),'d':0, 'c':'MIO[27]: data out'},
'data26': {'r':(10,10),'d':0, 'c':'MIO[26]: data out'},
'data25': {'r':( 9, 9),'d':0, 'c':'MIO[25]: data out'},
'data24': {'r':( 8, 8),'d':0, 'c':'MIO[24]: data out'},
'data23': {'r':( 7, 7),'d':0, 'c':'MIO[23]: data out'},
'data22': {'r':( 6, 6),'d':0, 'c':'MIO[22]: data out'},
'data21': {'r':( 5, 5),'d':0, 'c':'MIO[21]: data out'},
'data20': {'r':( 4, 4),'d':0, 'c':'MIO[20]: data out'},
'data19': {'r':( 3, 3),'d':0, 'c':'MIO[19]: data out'},
'data18': {'r':( 2, 2),'d':0, 'c':'MIO[18]: data out'},
'data17': {'r':( 1, 1),'d':0, 'c':'MIO[17]: data out'},
'data16': {'r':( 0, 0),'d':0, 'c':'MIO[16]: data out'}}},
'mask_data_1_lsw': {'OFFS': 0x008,'DFLT':0xffff0000,'RW':'RW','FORCE_DFLT':True,
'COMMENTS':'Maskable Output Data (GPIO MIO[32:47])',
'FIELDS':{
'mask47': {'r':(31,31),'d':1, 'c':'MIO[47]: 1 - keep, 0 - update, reads 0'},
'mask46': {'r':(30,30),'d':1, 'c':'MIO[46]: 1 - keep, 0 - update, reads 0'},
'mask45': {'r':(29,29),'d':1, 'c':'MIO[45]: 1 - keep, 0 - update, reads 0'},
'mask44': {'r':(28,28),'d':1, 'c':'MIO[44]: 1 - keep, 0 - update, reads 0'},
'mask43': {'r':(27,27),'d':1, 'c':'MIO[43]: 1 - keep, 0 - update, reads 0'},
'mask42': {'r':(26,26),'d':1, 'c':'MIO[42]: 1 - keep, 0 - update, reads 0'},
'mask41': {'r':(25,25),'d':1, 'c':'MIO[41]: 1 - keep, 0 - update, reads 0'},
'mask40': {'r':(24,24),'d':1, 'c':'MIO[40]: 1 - keep, 0 - update, reads 0'},
'mask39': {'r':(23,23),'d':1, 'c':'MIO[39]: 1 - keep, 0 - update, reads 0'},
'mask38': {'r':(22,22),'d':1, 'c':'MIO[38]: 1 - keep, 0 - update, reads 0'},
'mask37': {'r':(21,21),'d':1, 'c':'MIO[37]: 1 - keep, 0 - update, reads 0'},
'mask36': {'r':(20,20),'d':1, 'c':'MIO[36]: 1 - keep, 0 - update, reads 0'},
'mask35': {'r':(19,19),'d':1, 'c':'MIO[35]: 1 - keep, 0 - update, reads 0'},
'mask34': {'r':(18,18),'d':1, 'c':'MIO[34]: 1 - keep, 0 - update, reads 0'},
'mask33': {'r':(17,17),'d':1, 'c':'MIO[33]: 1 - keep, 0 - update, reads 0'},
'mask32': {'r':(16,16),'d':1, 'c':'MIO[32]: 1 - keep, 0 - update, reads 0'},
'data47': {'r':(15,15),'d':0, 'c':'MIO[47]: data out'},
'data46': {'r':(14,15),'d':0, 'c':'MIO[46]: data out'},
'data45': {'r':(13,15),'d':0, 'c':'MIO[45]: data out'},
'data44': {'r':(12,15),'d':0, 'c':'MIO[44]: data out'},
'data43': {'r':(11,15),'d':0, 'c':'MIO[43]: data out'},
'data42': {'r':(10,10),'d':0, 'c':'MIO[42]: data out'},
'data41': {'r':( 9, 9),'d':0, 'c':'MIO[41]: data out'},
'data40': {'r':( 8, 8),'d':0, 'c':'MIO[40]: data out'},
'data39': {'r':( 7, 7),'d':0, 'c':'MIO[39]: data out'},
'data38': {'r':( 6, 6),'d':0, 'c':'MIO[38]: data out'},
'data37': {'r':( 5, 5),'d':0, 'c':'MIO[37]: data out'},
'data36': {'r':( 4, 4),'d':0, 'c':'MIO[36]: data out'},
'data35': {'r':( 3, 3),'d':0, 'c':'MIO[35]: data out'},
'data34': {'r':( 2, 2),'d':0, 'c':'MIO[34]: data out'},
'data33': {'r':( 1, 1),'d':0, 'c':'MIO[33]: data out'},
'data32': {'r':( 0, 0),'d':0, 'c':'MIO[32]: data out'}}},
'mask_data_1_msw': {'OFFS': 0x00c,'DFLT':0xffff0000,'RW':'RW','FORCE_DFLT':True,
'COMMENTS':'Maskable Output Data (GPIO MIO[48:53])',
'FIELDS':{
'reserved1': {'r':(31,22),'d':0x3ff,'c':'reserved, reads 0'},
'mask53': {'r':(21,21),'d':1, 'c':'MIO[53]: 1 - keep, 0 - update, reads 0'},
'mask52': {'r':(20,20),'d':1, 'c':'MIO[52]: 1 - keep, 0 - update, reads 0'},
'mask51': {'r':(19,19),'d':1, 'c':'MIO[51]: 1 - keep, 0 - update, reads 0'},
'mask50': {'r':(18,18),'d':1, 'c':'MIO[50]: 1 - keep, 0 - update, reads 0'},
'mask49': {'r':(17,17),'d':1, 'c':'MIO[49]: 1 - keep, 0 - update, reads 0'},
'mask48': {'r':(16,16),'d':1, 'c':'MIO[48]: 1 - keep, 0 - update, reads 0'},
'reserved2': {'r':(15, 6),'d':0, 'c':'reserved, reads 0'},
'data53': {'r':( 5, 5),'d':0, 'c':'MIO[53]: data out'},
'data52': {'r':( 4, 4),'d':0, 'c':'MIO[52]: data out'},
'data51': {'r':( 3, 3),'d':0, 'c':'MIO[51]: data out'},
'data50': {'r':( 2, 2),'d':0, 'c':'MIO[50]: data out'},
'data49': {'r':( 1, 1),'d':0, 'c':'MIO[49]: data out'},
'data48': {'r':( 0, 0),'d':0, 'c':'MIO[48]: data out'}}},
'mask_data_2_lsw': {'OFFS': 0x010,'DFLT':0xffff0000,'RW':'RW','FORCE_DFLT':True,
'COMMENTS':'Maskable Output Data (GPIO EMIO[0:15])',
'FIELDS':{
'mask15': {'r':(31,31),'d':1, 'c':'EMIO[15]: 1 - keep, 0 - update, reads 0'},
'mask14': {'r':(30,30),'d':1, 'c':'EMIO[14]: 1 - keep, 0 - update, reads 0'},
'mask13': {'r':(29,29),'d':1, 'c':'EMIO[13]: 1 - keep, 0 - update, reads 0'},
'mask12': {'r':(28,28),'d':1, 'c':'EMIO[12]: 1 - keep, 0 - update, reads 0'},
'mask11': {'r':(27,27),'d':1, 'c':'EMIO[11]: 1 - keep, 0 - update, reads 0'},
'mask10': {'r':(26,26),'d':1, 'c':'EMIO[10]: 1 - keep, 0 - update, reads 0'},
'mask09': {'r':(25,25),'d':1, 'c':'EMIO[ 9]: 1 - keep, 0 - update, reads 0'},
'mask08': {'r':(24,24),'d':1, 'c':'EMIO[ 8]: 1 - keep, 0 - update, reads 0'},
'mask07': {'r':(23,23),'d':1, 'c':'EMIO[ 7]: 1 - keep, 0 - update, reads 0'},
'mask06': {'r':(22,22),'d':1, 'c':'EMIO[ 6]: 1 - keep, 0 - update, reads 0'},
'mask05': {'r':(21,21),'d':1, 'c':'EMIO[ 5]: 1 - keep, 0 - update, reads 0'},
'mask04': {'r':(20,20),'d':1, 'c':'EMIO[ 4]: 1 - keep, 0 - update, reads 0'},
'mask03': {'r':(19,19),'d':1, 'c':'EMIO[ 3]: 1 - keep, 0 - update, reads 0'},
'mask02': {'r':(18,18),'d':1, 'c':'EMIO[ 2]: 1 - keep, 0 - update, reads 0'},
'mask01': {'r':(17,17),'d':1, 'c':'EMIO[ 1]: 1 - keep, 0 - update, reads 0'},
'mask00': {'r':(16,16),'d':1, 'c':'EMIO[ 0]: 1 - keep, 0 - update, reads 0'},
'data15': {'r':(15,15),'d':0, 'c':'EMIO[15]: data out'},
'data14': {'r':(14,15),'d':0, 'c':'EMIO[14]: data out'},
'data13': {'r':(13,15),'d':0, 'c':'EMIO[13]: data out'},
'data12': {'r':(12,15),'d':0, 'c':'EMIO[12]: data out'},
'data11': {'r':(11,15),'d':0, 'c':'EMIO[11]: data out'},
'data10': {'r':(10,10),'d':0, 'c':'EMIO[10]: data out'},
'data09': {'r':( 9, 9),'d':0, 'c':'EMIO[ 9]: data out'},
'data08': {'r':( 8, 8),'d':0, 'c':'EMIO[ 8]: data out'},
'data07': {'r':( 7, 7),'d':0, 'c':'EMIO[ 7]: data out'},
'data06': {'r':( 6, 6),'d':0, 'c':'EMIO[ 6]: data out'},
'data05': {'r':( 5, 5),'d':0, 'c':'EMIO[ 5]: data out'},
'data04': {'r':( 4, 4),'d':0, 'c':'EMIO[ 4]: data out'},
'data03': {'r':( 3, 3),'d':0, 'c':'EMIO[ 3]: data out'},
'data02': {'r':( 2, 2),'d':0, 'c':'EMIO[ 2]: data out'},
'data01': {'r':( 1, 1),'d':0, 'c':'EMIO[ 1]: data out'},
'data00': {'r':( 0, 0),'d':0, 'c':'EMIO[ 0]: data out'}}},
'mask_data_2_msw': {'OFFS': 0x014,'DFLT':0xffff0000,'RW':'RW','FORCE_DFLT':True,
'COMMENTS':'Maskable Output Data (GPIO EMIO[16:31])',
'FIELDS':{
'mask31': {'r':(31,31),'d':1, 'c':'EMIO[31]: 1 - keep, 0 - update, reads 0'},
'mask30': {'r':(30,30),'d':1, 'c':'EMIO[30]: 1 - keep, 0 - update, reads 0'},
'mask29': {'r':(29,29),'d':1, 'c':'EMIO[29]: 1 - keep, 0 - update, reads 0'},
'mask28': {'r':(28,28),'d':1, 'c':'EMIO[28]: 1 - keep, 0 - update, reads 0'},
'mask27': {'r':(27,27),'d':1, 'c':'EMIO[27]: 1 - keep, 0 - update, reads 0'},
'mask26': {'r':(26,26),'d':1, 'c':'EMIO[26]: 1 - keep, 0 - update, reads 0'},
'mask25': {'r':(25,25),'d':1, 'c':'EMIO[25]: 1 - keep, 0 - update, reads 0'},
'mask24': {'r':(24,24),'d':1, 'c':'EMIO[24]: 1 - keep, 0 - update, reads 0'},
'mask23': {'r':(23,23),'d':1, 'c':'EMIO[23]: 1 - keep, 0 - update, reads 0'},
'mask22': {'r':(22,22),'d':1, 'c':'EMIO[22]: 1 - keep, 0 - update, reads 0'},
'mask21': {'r':(21,21),'d':1, 'c':'EMIO[21]: 1 - keep, 0 - update, reads 0'},
'mask20': {'r':(20,20),'d':1, 'c':'EMIO[20]: 1 - keep, 0 - update, reads 0'},
'mask19': {'r':(19,19),'d':1, 'c':'EMIO[19]: 1 - keep, 0 - update, reads 0'},
'mask18': {'r':(18,18),'d':1, 'c':'EMIO[18]: 1 - keep, 0 - update, reads 0'},
'mask17': {'r':(17,17),'d':1, 'c':'EMIO[17]: 1 - keep, 0 - update, reads 0'},
'mask16': {'r':(16,16),'d':1, 'c':'EMIO[16]: 1 - keep, 0 - update, reads 0'},
'data31': {'r':(15,15),'d':0, 'c':'EMIO[31]: data out'},
'data30': {'r':(14,15),'d':0, 'c':'EMIO[30]: data out'},
'data29': {'r':(13,15),'d':0, 'c':'EMIO[29]: data out'},
'data28': {'r':(12,15),'d':0, 'c':'EMIO[28]: data out'},
'data27': {'r':(11,15),'d':0, 'c':'EMIO[27]: data out'},
'data26': {'r':(10,10),'d':0, 'c':'EMIO[26]: data out'},
'data25': {'r':( 9, 9),'d':0, 'c':'EMIO[25]: data out'},
'data24': {'r':( 8, 8),'d':0, 'c':'EMIO[24]: data out'},
'data23': {'r':( 7, 7),'d':0, 'c':'EMIO[23]: data out'},
'data22': {'r':( 6, 6),'d':0, 'c':'EMIO[22]: data out'},
'data21': {'r':( 5, 5),'d':0, 'c':'EMIO[21]: data out'},
'data20': {'r':( 4, 4),'d':0, 'c':'EMIO[20]: data out'},
'data19': {'r':( 3, 3),'d':0, 'c':'EMIO[19]: data out'},
'data18': {'r':( 2, 2),'d':0, 'c':'EMIO[18]: data out'},
'data17': {'r':( 1, 1),'d':0, 'c':'EMIO[17]: data out'},
'data16': {'r':( 0, 0),'d':0, 'c':'EMIO[16]: data out'}}},
'mask_data_3_lsw': {'OFFS': 0x018,'DFLT':0xffff0000,'RW':'RW','FORCE_DFLT':True,
'COMMENTS':'Maskable Output Data (GPIO EMIO[32:47])',
'FIELDS':{
'mask47': {'r':(31,31),'d':1, 'c':'EMIO[47]: 1 - keep, 0 - update, reads 0'},
'mask46': {'r':(30,30),'d':1, 'c':'EMIO[46]: 1 - keep, 0 - update, reads 0'},
'mask45': {'r':(29,29),'d':1, 'c':'EMIO[45]: 1 - keep, 0 - update, reads 0'},
'mask44': {'r':(28,28),'d':1, 'c':'EMIO[44]: 1 - keep, 0 - update, reads 0'},
'mask43': {'r':(27,27),'d':1, 'c':'EMIO[43]: 1 - keep, 0 - update, reads 0'},
'mask42': {'r':(26,26),'d':1, 'c':'EMIO[42]: 1 - keep, 0 - update, reads 0'},
'mask41': {'r':(25,25),'d':1, 'c':'EMIO[41]: 1 - keep, 0 - update, reads 0'},
'mask40': {'r':(24,24),'d':1, 'c':'EMIO[40]: 1 - keep, 0 - update, reads 0'},
'mask39': {'r':(23,23),'d':1, 'c':'EMIO[39]: 1 - keep, 0 - update, reads 0'},
'mask38': {'r':(22,22),'d':1, 'c':'EMIO[38]: 1 - keep, 0 - update, reads 0'},
'mask37': {'r':(21,21),'d':1, 'c':'EMIO[37]: 1 - keep, 0 - update, reads 0'},
'mask36': {'r':(20,20),'d':1, 'c':'EMIO[36]: 1 - keep, 0 - update, reads 0'},
'mask35': {'r':(19,19),'d':1, 'c':'EMIO[35]: 1 - keep, 0 - update, reads 0'},
'mask34': {'r':(18,18),'d':1, 'c':'EMIO[34]: 1 - keep, 0 - update, reads 0'},
'mask33': {'r':(17,17),'d':1, 'c':'EMIO[33]: 1 - keep, 0 - update, reads 0'},
'mask32': {'r':(16,16),'d':1, 'c':'EMIO[32]: 1 - keep, 0 - update, reads 0'},
'data47': {'r':(15,15),'d':0, 'c':'EMIO[47]: data out'},
'data46': {'r':(14,15),'d':0, 'c':'EMIO[46]: data out'},
'data45': {'r':(13,15),'d':0, 'c':'EMIO[45]: data out'},
'data44': {'r':(12,15),'d':0, 'c':'EMIO[44]: data out'},
'data43': {'r':(11,15),'d':0, 'c':'EMIO[43]: data out'},
'data42': {'r':(10,10),'d':0, 'c':'EMIO[42]: data out'},
'data41': {'r':( 9, 9),'d':0, 'c':'EMIO[41]: data out'},
'data40': {'r':( 8, 8),'d':0, 'c':'EMIO[40]: data out'},
'data39': {'r':( 7, 7),'d':0, 'c':'EMIO[39]: data out'},
'data38': {'r':( 6, 6),'d':0, 'c':'EMIO[38]: data out'},
'data37': {'r':( 5, 5),'d':0, 'c':'EMIO[37]: data out'},
'data36': {'r':( 4, 4),'d':0, 'c':'EMIO[36]: data out'},
'data35': {'r':( 3, 3),'d':0, 'c':'EMIO[35]: data out'},
'data34': {'r':( 2, 2),'d':0, 'c':'EMIO[34]: data out'},
'data33': {'r':( 1, 1),'d':0, 'c':'EMIO[33]: data out'},
'data32': {'r':( 0, 0),'d':0, 'c':'EMIO[32]: data out'}}},
'mask_data_3_msw': {'OFFS': 0x01c,'DFLT':0xffff0000,'RW':'RW','FORCE_DFLT':True,
'COMMENTS':'Maskable Output Data (GPIO EMIO[48:63])',
'FIELDS':{
'mask63': {'r':(31,31),'d':1, 'c':'EMIO[63]: 1 - keep, 0 - update, reads 0'},
'mask62': {'r':(30,30),'d':1, 'c':'EMIO[62]: 1 - keep, 0 - update, reads 0'},
'mask61': {'r':(29,29),'d':1, 'c':'EMIO[61]: 1 - keep, 0 - update, reads 0'},
'mask60': {'r':(28,28),'d':1, 'c':'EMIO[60]: 1 - keep, 0 - update, reads 0'},
'mask59': {'r':(27,27),'d':1, 'c':'EMIO[59]: 1 - keep, 0 - update, reads 0'},
'mask58': {'r':(26,26),'d':1, 'c':'EMIO[58]: 1 - keep, 0 - update, reads 0'},
'mask57': {'r':(25,25),'d':1, 'c':'EMIO[57]: 1 - keep, 0 - update, reads 0'},
'mask56': {'r':(24,24),'d':1, 'c':'EMIO[56]: 1 - keep, 0 - update, reads 0'},
'mask55': {'r':(23,23),'d':1, 'c':'EMIO[55]: 1 - keep, 0 - update, reads 0'},
'mask54': {'r':(22,22),'d':1, 'c':'EMIO[54]: 1 - keep, 0 - update, reads 0'},
'mask53': {'r':(21,21),'d':1, 'c':'EMIO[53]: 1 - keep, 0 - update, reads 0'},
'mask52': {'r':(20,20),'d':1, 'c':'EMIO[52]: 1 - keep, 0 - update, reads 0'},
'mask51': {'r':(19,19),'d':1, 'c':'EMIO[51]: 1 - keep, 0 - update, reads 0'},
'mask50': {'r':(18,18),'d':1, 'c':'EMIO[50]: 1 - keep, 0 - update, reads 0'},
'mask49': {'r':(17,17),'d':1, 'c':'EMIO[49]: 1 - keep, 0 - update, reads 0'},
'mask48': {'r':(16,16),'d':1, 'c':'EMIO[48]: 1 - keep, 0 - update, reads 0'},
'data63': {'r':(15,15),'d':0, 'c':'EMIO[63]: data out'},
'data62': {'r':(14,15),'d':0, 'c':'EMIO[62]: data out'},
'data61': {'r':(13,15),'d':0, 'c':'EMIO[61]: data out'},
'data60': {'r':(12,15),'d':0, 'c':'EMIO[60]: data out'},
'data59': {'r':(11,15),'d':0, 'c':'EMIO[59]: data out'},
'data58': {'r':(10,10),'d':0, 'c':'EMIO[58]: data out'},
'data57': {'r':( 9, 9),'d':0, 'c':'EMIO[57]: data out'},
'data56': {'r':( 8, 8),'d':0, 'c':'EMIO[56]: data out'},
'data55': {'r':( 7, 7),'d':0, 'c':'EMIO[55]: data out'},
'data54': {'r':( 6, 6),'d':0, 'c':'EMIO[54]: data out'},
'data53': {'r':( 5, 5),'d':0, 'c':'EMIO[53]: data out'},
'data52': {'r':( 4, 4),'d':0, 'c':'EMIO[52]: data out'},
'data51': {'r':( 3, 3),'d':0, 'c':'EMIO[51]: data out'},
'data50': {'r':( 2, 2),'d':0, 'c':'EMIO[50]: data out'},
'data49': {'r':( 1, 1),'d':0, 'c':'EMIO[49]: data out'},
'data48': {'r':( 0, 0),'d':0, 'c':'EMIO[48]: data out'}}},
'data_0_ro': {'OFFS': 0x060,'RW':'R',
'COMMENTS':'Read only data from the MIO pins [0:31]',
'FIELDS':{
'data_ro_mio_00_31': {'r':(0, 31),'m':'R','c':'Data on the I/O pins MIO[0:31]'}}},
'data_1_ro': {'OFFS': 0x064,'RW':'R',
'COMMENTS':'Read only data from the MIO pins [0:31]',
'FIELDS':{
'data_ro_mio_32_53': {'r':(0, 21),'m':'R','c':'Data on the I/O pins MIO[32:53]'}}},
'data_2_ro': {'OFFS': 0x068,'DFLT':0x0,'RW':'R',
'COMMENTS':'Read only data from the MIO pins [0:31]',
'FIELDS':{
'data_ro_emio_00_31': {'r':(0, 31),'d':0,'m':'R','c':'Data on the I/O pins EMIO[0:31]'}}},
'data_3_ro': {'OFFS': 0x06c,'DFLT':0x0,'RW':'R',
'COMMENTS':'Read only data from the MIO pins [0:31]',
'FIELDS':{
'data_ro_emio_32_63': {'r':(0, 31),'d':0,'m':'R','c':'Data on the I/O pins EMIO[32:63]'}}},
'dirm_0': {'OFFS': 0x204,'RW':'RW',
'COMMENTS':'Output direction for MIO pins [0:31]',
'FIELDS':{
'dirm_31': {'r':(31,31),'d':0,'m':'RW','c':'Direction of GPIO[31]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_30': {'r':(30,30),'d':0,'m':'RW','c':'Direction of GPIO[30]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_29': {'r':(29,29),'d':0,'m':'RW','c':'Direction of GPIO[29]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_28': {'r':(28,28),'d':0,'m':'RW','c':'Direction of GPIO[28]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_27': {'r':(27,27),'d':0,'m':'RW','c':'Direction of GPIO[27]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_26': {'r':(26,26),'d':0,'m':'RW','c':'Direction of GPIO[26]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_25': {'r':(25,25),'d':0,'m':'RW','c':'Direction of GPIO[25]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_24': {'r':(24,24),'d':0,'m':'RW','c':'Direction of GPIO[24]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_23': {'r':(23,23),'d':0,'m':'RW','c':'Direction of GPIO[23]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_22': {'r':(22,22),'d':0,'m':'RW','c':'Direction of GPIO[22]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_21': {'r':(21,21),'d':0,'m':'RW','c':'Direction of GPIO[21]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_20': {'r':(20,20),'d':0,'m':'RW','c':'Direction of GPIO[20]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_19': {'r':(19,19),'d':0,'m':'RW','c':'Direction of GPIO[19]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_18': {'r':(18,18),'d':0,'m':'RW','c':'Direction of GPIO[18]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_17': {'r':(17,17),'d':0,'m':'RW','c':'Direction of GPIO[17]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_16': {'r':(16,16),'d':0,'m':'RW','c':'Direction of GPIO[16]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_15': {'r':(15,15),'d':0,'m':'RW','c':'Direction of GPIO[15]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_14': {'r':(14,14),'d':0,'m':'RW','c':'Direction of GPIO[14]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_13': {'r':(13,13),'d':0,'m':'RW','c':'Direction of GPIO[13]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_12': {'r':(12,12),'d':0,'m':'RW','c':'Direction of GPIO[12]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_11': {'r':(11,11),'d':0,'m':'RW','c':'Direction of GPIO111]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_10': {'r':(10,10),'d':0,'m':'RW','c':'Direction of GPIO[10]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_09': {'r':( 9, 9),'d':0,'m':'RW','c':'Direction of GPIO[ 9]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_08': {'r':( 8, 8),'d':0,'m':'RW','c':'Direction of GPIO[ 8]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_07': {'r':( 7, 7),'d':0,'m':'RW','c':'Direction of GPIO[ 7]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_06': {'r':( 6, 6),'d':0,'m':'RW','c':'Direction of GPIO[ 6]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_05': {'r':( 5, 5),'d':0,'m':'RW','c':'Direction of GPIO[ 5]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_04': {'r':( 4, 4),'d':0,'m':'RW','c':'Direction of GPIO[ 4]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_03': {'r':( 3, 3),'d':0,'m':'RW','c':'Direction of GPIO[ 3]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_02': {'r':( 2, 2),'d':0,'m':'RW','c':'Direction of GPIO[ 2]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_01': {'r':( 1, 1),'d':0,'m':'RW','c':'Direction of GPIO[ 1]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_00': {'r':( 0, 0),'d':0,'m':'RW','c':'Direction of GPIO[ 0]. 0 - input (resets and disables corresponding output bit), 1 - output'}}},
'oen_0': {'OFFS': 0x208,'RW':'RW',
'COMMENTS':'Output enable for MIO pins [0:31] (SLCR tristate should be disabled for this register bits to be active)',
'FIELDS':{
'oe_31': {'r':(31,31),'d':0,'m':'RW','c':'Output enable for GPIO[31]: 1 - enabled, 0 - disabled'},
'oe_30': {'r':(30,30),'d':0,'m':'RW','c':'Output enable for GPIO[30]: 1 - enabled, 0 - disabled'},
'oe_29': {'r':(29,29),'d':0,'m':'RW','c':'Output enable for GPIO[29]: 1 - enabled, 0 - disabled'},
'oe_28': {'r':(28,28),'d':0,'m':'RW','c':'Output enable for GPIO[28]: 1 - enabled, 0 - disabled'},
'oe_27': {'r':(27,27),'d':0,'m':'RW','c':'Output enable for GPIO[27]: 1 - enabled, 0 - disabled'},
'oe_26': {'r':(26,26),'d':0,'m':'RW','c':'Output enable for GPIO[26]: 1 - enabled, 0 - disabled'},
'oe_25': {'r':(25,25),'d':0,'m':'RW','c':'Output enable for GPIO[25]: 1 - enabled, 0 - disabled'},
'oe_24': {'r':(24,24),'d':0,'m':'RW','c':'Output enable for GPIO[24]: 1 - enabled, 0 - disabled'},
'oe_23': {'r':(23,23),'d':0,'m':'RW','c':'Output enable for GPIO[23]: 1 - enabled, 0 - disabled'},
'oe_22': {'r':(22,22),'d':0,'m':'RW','c':'Output enable for GPIO[22]: 1 - enabled, 0 - disabled'},
'oe_21': {'r':(21,21),'d':0,'m':'RW','c':'Output enable for GPIO[21]: 1 - enabled, 0 - disabled'},
'oe_20': {'r':(20,20),'d':0,'m':'RW','c':'Output enable for GPIO[20]: 1 - enabled, 0 - disabled'},
'oe_19': {'r':(19,19),'d':0,'m':'RW','c':'Output enable for GPIO[19]: 1 - enabled, 0 - disabled'},
'oe_18': {'r':(18,18),'d':0,'m':'RW','c':'Output enable for GPIO[18]: 1 - enabled, 0 - disabled'},
'oe_17': {'r':(17,17),'d':0,'m':'RW','c':'Output enable for GPIO[17]: 1 - enabled, 0 - disabled'},
'oe_16': {'r':(16,16),'d':0,'m':'RW','c':'Output enable for GPIO[16]: 1 - enabled, 0 - disabled'},
'oe_15': {'r':(15,15),'d':0,'m':'RW','c':'Output enable for GPIO[15]: 1 - enabled, 0 - disabled'},
'oe_14': {'r':(14,14),'d':0,'m':'RW','c':'Output enable for GPIO[14]: 1 - enabled, 0 - disabled'},
'oe_13': {'r':(13,13),'d':0,'m':'RW','c':'Output enable for GPIO[13]: 1 - enabled, 0 - disabled'},
'oe_12': {'r':(12,12),'d':0,'m':'RW','c':'Output enable for GPIO[12]: 1 - enabled, 0 - disabled'},
'oe_11': {'r':(11,11),'d':0,'m':'RW','c':'Output enable for GPIO[11]: 1 - enabled, 0 - disabled'},
'oe_10': {'r':(10,10),'d':0,'m':'RW','c':'Output enable for GPIO[10]: 1 - enabled, 0 - disabled'},
'oe_09': {'r':( 9, 9),'d':0,'m':'RW','c':'Output enable for GPIO[ 9]: 1 - enabled, 0 - disabled'},
'oe_08': {'r':( 8, 8),'d':0,'m':'RW','c':'Output enable for GPIO[ 8]: 1 - enabled, 0 - disabled'},
'oe_07': {'r':( 7, 7),'d':0,'m':'RW','c':'Output enable for GPIO[ 7]: 1 - enabled, 0 - disabled'},
'oe_06': {'r':( 6, 6),'d':0,'m':'RW','c':'Output enable for GPIO[ 6]: 1 - enabled, 0 - disabled'},
'oe_05': {'r':( 5, 5),'d':0,'m':'RW','c':'Output enable for GPIO[ 5]: 1 - enabled, 0 - disabled'},
'oe_04': {'r':( 4, 4),'d':0,'m':'RW','c':'Output enable for GPIO[ 4]: 1 - enabled, 0 - disabled'},
'oe_03': {'r':( 3, 3),'d':0,'m':'RW','c':'Output enable for GPIO[ 3]: 1 - enabled, 0 - disabled'},
'oe_02': {'r':( 2, 2),'d':0,'m':'RW','c':'Output enable for GPIO[ 2]: 1 - enabled, 0 - disabled'},
'oe_01': {'r':( 1, 1),'d':0,'m':'RW','c':'Output enable for GPIO[ 1]: 1 - enabled, 0 - disabled'},
'oe_00': {'r':( 0, 0),'d':0,'m':'RW','c':'Output enable for GPIO[ 0]: 1 - enabled, 0 - disabled'}}},
'dirm_1': {'OFFS': 0x244,'RW':'RW',
'COMMENTS':'Output direction for MIO pins [32:53]',
'FIELDS':{
'dirm_53': {'r':(21,21),'d':0,'m':'RW','c':'Direction of GPIO[53]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_52': {'r':(20,20),'d':0,'m':'RW','c':'Direction of GPIO[52]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_51': {'r':(19,19),'d':0,'m':'RW','c':'Direction of GPIO[51]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_50': {'r':(18,18),'d':0,'m':'RW','c':'Direction of GPIO[50]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_49': {'r':(17,17),'d':0,'m':'RW','c':'Direction of GPIO[49]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_48': {'r':(16,16),'d':0,'m':'RW','c':'Direction of GPIO[48]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_47': {'r':(15,15),'d':0,'m':'RW','c':'Direction of GPIO[47]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_46': {'r':(14,14),'d':0,'m':'RW','c':'Direction of GPIO[46]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_45': {'r':(13,13),'d':0,'m':'RW','c':'Direction of GPIO[45]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_44': {'r':(12,12),'d':0,'m':'RW','c':'Direction of GPIO[44]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_43': {'r':(11,11),'d':0,'m':'RW','c':'Direction of GPIO143]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_42': {'r':(10,10),'d':0,'m':'RW','c':'Direction of GPIO[42]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_41': {'r':( 9, 9),'d':0,'m':'RW','c':'Direction of GPIO[41]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_40': {'r':( 8, 8),'d':0,'m':'RW','c':'Direction of GPIO[40]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_39': {'r':( 7, 7),'d':0,'m':'RW','c':'Direction of GPIO[49]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_38': {'r':( 6, 6),'d':0,'m':'RW','c':'Direction of GPIO[48]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_37': {'r':( 5, 5),'d':0,'m':'RW','c':'Direction of GPIO[47]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_36': {'r':( 4, 4),'d':0,'m':'RW','c':'Direction of GPIO[46]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_35': {'r':( 3, 3),'d':0,'m':'RW','c':'Direction of GPIO[45]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_34': {'r':( 2, 2),'d':0,'m':'RW','c':'Direction of GPIO[44]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_33': {'r':( 1, 1),'d':0,'m':'RW','c':'Direction of GPIO[43]. 0 - input (resets and disables corresponding output bit), 1 - output'},
'dirm_32': {'r':( 0, 0),'d':0,'m':'RW','c':'Direction of GPIO[42]. 0 - input (resets and disables corresponding output bit), 1 - output'}}},
'oen_1': {'OFFS': 0x248,'RW':'RW',
'COMMENTS':'Output enable for MIO pins [32:53] (SLCR tristate should be disabled for this register bits to be active)',
'FIELDS':{
'oe_53': {'r':(21,21),'d':0,'m':'RW','c':'Output enable for GPIO[53]: 1 - enabled, 0 - disabled'},
'oe_52': {'r':(20,20),'d':0,'m':'RW','c':'Output enable for GPIO[52]: 1 - enabled, 0 - disabled'},
'oe_51': {'r':(19,19),'d':0,'m':'RW','c':'Output enable for GPIO[51]: 1 - enabled, 0 - disabled'},
'oe_50': {'r':(18,18),'d':0,'m':'RW','c':'Output enable for GPIO[50]: 1 - enabled, 0 - disabled'},
'oe_49': {'r':(17,17),'d':0,'m':'RW','c':'Output enable for GPIO[49]: 1 - enabled, 0 - disabled'},
'oe_48': {'r':(16,16),'d':0,'m':'RW','c':'Output enable for GPIO[48]: 1 - enabled, 0 - disabled'},
'oe_47': {'r':(15,15),'d':0,'m':'RW','c':'Output enable for GPIO[47]: 1 - enabled, 0 - disabled'},
'oe_46': {'r':(14,14),'d':0,'m':'RW','c':'Output enable for GPIO[46]: 1 - enabled, 0 - disabled'},
'oe_45': {'r':(13,13),'d':0,'m':'RW','c':'Output enable for GPIO[45]: 1 - enabled, 0 - disabled'},
'oe_44': {'r':(12,12),'d':0,'m':'RW','c':'Output enable for GPIO[44]: 1 - enabled, 0 - disabled'},
'oe_43': {'r':(11,11),'d':0,'m':'RW','c':'Output enable for GPIO[43]: 1 - enabled, 0 - disabled'},
'oe_42': {'r':(10,10),'d':0,'m':'RW','c':'Output enable for GPIO[42]: 1 - enabled, 0 - disabled'},
'oe_41': {'r':( 9, 9),'d':0,'m':'RW','c':'Output enable for GPIO[41]: 1 - enabled, 0 - disabled'},
'oe_40': {'r':( 8, 8),'d':0,'m':'RW','c':'Output enable for GPIO[40]: 1 - enabled, 0 - disabled'},
'oe_39': {'r':( 7, 7),'d':0,'m':'RW','c':'Output enable for GPIO[39]: 1 - enabled, 0 - disabled'},
'oe_38': {'r':( 6, 6),'d':0,'m':'RW','c':'Output enable for GPIO[38]: 1 - enabled, 0 - disabled'},
'oe_37': {'r':( 5, 5),'d':0,'m':'RW','c':'Output enable for GPIO[37]: 1 - enabled, 0 - disabled'},
'oe_36': {'r':( 4, 4),'d':0,'m':'RW','c':'Output enable for GPIO[36]: 1 - enabled, 0 - disabled'},
'oe_35': {'r':( 3, 3),'d':0,'m':'RW','c':'Output enable for GPIO[35]: 1 - enabled, 0 - disabled'},
'oe_34': {'r':( 2, 2),'d':0,'m':'RW','c':'Output enable for GPIO[34]: 1 - enabled, 0 - disabled'},
'oe_33': {'r':( 1, 1),'d':0,'m':'RW','c':'Output enable for GPIO[33]: 1 - enabled, 0 - disabled'},
'oe_32': {'r':( 0, 0),'d':0,'m':'RW','c':'Output enable for GPIO[32]: 1 - enabled, 0 - disabled'}}},
}
ezynq_mio.py
View file @ 27df5bb0
...@@ -25,6 +25,7 @@ __status__ = "Development" ...@@ -25,6 +25,7 @@ __status__ = "Development"
import ezynq_registers import ezynq_registers
#import ezynq_feature_config #import ezynq_feature_config
import ezynq_slcr_clk_def import ezynq_slcr_clk_def
import ezynq_gpio_defs
MIO_ATTRIBS=['SLOW','FAST','PULLUP','NOPULLUP'] MIO_ATTRIBS=['SLOW','FAST','PULLUP','NOPULLUP']
MIO_TEMPLATES = { MIO_TEMPLATES = {
...@@ -284,9 +285,11 @@ class EzynqMIO: ...@@ -284,9 +285,11 @@ class EzynqMIO:
def __init__(self, verbosity, qualifier_char, regs_masked, permit_undefined_bits=False): def __init__(self, verbosity, qualifier_char, regs_masked, permit_undefined_bits=False):
# print ezynq_slcr_clk_def.MIO_PINS_DEFS # print ezynq_slcr_clk_def.MIO_PINS_DEFS
self.MIO_PINS_DEFS= ezynq_slcr_clk_def.SLCR_DEFS #combined self.MIO_PINS_DEFS= ezynq_slcr_clk_def.SLCR_DEFS #combined
self.GPIO_DEFS=ezynq_gpio_defs.GPIO_DEFS
self.qualifier_char=qualifier_char self.qualifier_char=qualifier_char
self.verbosity= verbosity self.verbosity= verbosity
self.slcr_register_set= ezynq_registers.EzynqRegisters(self.MIO_PINS_DEFS,0,regs_masked,permit_undefined_bits) self.slcr_register_set= ezynq_registers.EzynqRegisters(self.MIO_PINS_DEFS,0,regs_masked,permit_undefined_bits)
self.gpio_register_set= ezynq_registers.EzynqRegisters(self.GPIO_DEFS,0,regs_masked,permit_undefined_bits)
def generate_led_off_on(self, mio_pin): def generate_led_off_on(self, mio_pin):
# generate code to be included in u-boot for debugging early boot stages # generate code to be included in u-boot for debugging early boot stages
...@@ -617,7 +620,7 @@ class EzynqMIO: ...@@ -617,7 +620,7 @@ class EzynqMIO:
print 'Invalid MIO pin polarity in',attr['PREFIX']+str(pin),'=',value print 'Invalid MIO pin polarity in',attr['PREFIX']+str(pin),'=',value
print 'Polarity can only be IN, OUT or BIDIR' print 'Polarity can only be IN, OUT or BIDIR'
exit (ERROR_DEFS['INOUT']) exit (ERROR_DEFS['INOUT'])
if (pin==7) or (pin==8) and (value!='OUT'): if ((pin==7) or (pin==8)) and (value!='OUT'):
print 'Invalid MIO pin polarity in',attr['PREFIX']+str(pin),'=',value print 'Invalid MIO pin polarity in',attr['PREFIX']+str(pin),'=',value
print 'Polarity for MIO pins 7 and 8 can only be OUT' print 'Polarity for MIO pins 7 and 8 can only be OUT'
exit (ERROR_DEFS['INOUT']) exit (ERROR_DEFS['INOUT'])
...@@ -664,6 +667,42 @@ class EzynqMIO: ...@@ -664,6 +667,42 @@ class EzynqMIO:
return self.slcr_register_set.get_register_sets(True,True) return self.slcr_register_set.get_register_sets(True,True)
def setregs_gpio(self,current_reg_sets,force=True):
mask_data_regs_mio=('mask_data_0_lsw','mask_data_0_msw','mask_data_1_lsw','mask_data_1_msw');
self.slcr_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
# first find out which groups of 16 pins are outputs (if any)
for i,mio_pin in enumerate(self.mio):
if ('DATA_OUT' in mio_pin) or (('INOUT' in mio_pin) and (mio_pin['INOUT'] != 'IN')):
break
else:
return current_reg_sets # no outputs to program
# 1. Program SLCR (should be already done, now just no clean up after debug LED unknown state)
for i,mio_pin in enumerate(self.mio):
if ('DATA_OUT' in mio_pin) or (('INOUT' in mio_pin) and (mio_pin['INOUT'] != 'IN')):
self.slcr_register_set.set_bitfields('mio_pin_%02i'%i,(('tri_enable',0),),force) # disable tristate
reg_sets=self.slcr_register_set.get_register_sets(True,True)
self.gpio_register_set.set_initial_state(reg_sets, True) #continuing with GPIO registers
# 2. set DIRM for outputs
for i,mio_pin in enumerate(self.mio):
if ('DATA_OUT' in mio_pin) or (('INOUT' in mio_pin) and (mio_pin['INOUT'] == 'OUT')):
self.gpio_register_set.set_bitfields('dirm_%i'%(i/32),
(('dirm_%02i'%i,1),),force) # direction - output
self.gpio_register_set.flush()
# 3. set data for outputs
for i,mio_pin in enumerate(self.mio):
if 'DATA_OUT' in mio_pin:
self.gpio_register_set.set_bitfields(mask_data_regs_mio[i/16],
(('mask%02i'%i,0), # enable setting bit
('data%02i'%i,mio_pin['DATA_OUT']!=0)),force) # data to set
self.gpio_register_set.flush()
# 4. Output enable
for i,mio_pin in enumerate(self.mio):
if ('DATA_OUT' in mio_pin) or (('INOUT' in mio_pin) and (mio_pin['INOUT'] == 'OUT')):
self.gpio_register_set.set_bitfields('oen_%i'%(i/32),
(('oe_%02i'%i,1),),force) # enable output
return self.gpio_register_set.get_register_sets(True,True)
# Just add to the HTML output # Just add to the HTML output
def output_mio(self,f,MIO_HTML_MASK): def output_mio(self,f,MIO_HTML_MASK):
# initialize register_set # initialize register_set
......
ezynq_registers.py
View file @ 27df5bb0
...@@ -80,6 +80,7 @@ def print_html_registers(html_file, reg_sets, from_index, show_bit_fields=True, ...@@ -80,6 +80,7 @@ def print_html_registers(html_file, reg_sets, from_index, show_bit_fields=True,
prev_sdata='-' prev_sdata='-'
new_data=((old_data ^ data) & mask) ^ old_data new_data=((old_data ^ data) & mask) ^ old_data
new_mask= old_mask | mask new_mask= old_mask | mask
if not 'FORCE_DFLT' in r_def: # do not save state if force default (always start from default value) is in effect
current_reg_state[addr]=(new_data,new_mask) current_reg_state[addr]=(new_data,new_mask)
else: else:
new_data= data new_data= data
...@@ -179,6 +180,14 @@ def accumulate_reg_data(reg_sets,accumulate_mask=False): ...@@ -179,6 +180,14 @@ def accumulate_reg_data(reg_sets,accumulate_mask=False):
cumulative_regs=[() for _ in reg_sets] cumulative_regs=[() for _ in reg_sets]
for index, (op, addr, data, mask, module_name, register_name, r_def) in enumerate (reg_sets): for index, (op, addr, data, mask, module_name, register_name, r_def) in enumerate (reg_sets):
if (op == 's') and (addr in initial_state): # only accumulate register set operations, not wait for equal ('=') or wait for not-equal ('!') if (op == 's') and (addr in initial_state): # only accumulate register set operations, not wait for equal ('=') or wait for not-equal ('!')
if 'FORCE_DFLT' in r_def:
#is old_mask=0 enough? no need for old_data
try:
old_data=r_def['DFLT']
except:
old_data=0
old_mask=0
else:
old_data,old_mask=initial_state[addr] old_data,old_mask=initial_state[addr]
data=((old_data ^ data) & mask) ^ old_data data=((old_data ^ data) & mask) ^ old_data
if accumulate_mask: if accumulate_mask:
...@@ -232,6 +241,8 @@ class EzynqRegisters: ...@@ -232,6 +241,8 @@ class EzynqRegisters:
def set_initial_state(self,added_reg_sets, init=True): def set_initial_state(self,added_reg_sets, init=True):
# new_sets.append((op,addr,data,mask,self.module_name,register_name,self.defs[register_name]))
if init: if init:
self.initial_state={} self.initial_state={}
self.previous_reg_sets=[] self.previous_reg_sets=[]
...@@ -242,13 +253,12 @@ class EzynqRegisters: ...@@ -242,13 +253,12 @@ class EzynqRegisters:
if not added_reg_sets: if not added_reg_sets:
return return
self.previous_reg_sets+=added_reg_sets # appends, not overwrites self.previous_reg_sets+=added_reg_sets # appends, not overwrites
for op,addr,data,mask,_,_,_ in added_reg_sets: # Do not need to care about default values - they will have 0 in the mask bits. for op,addr,data,mask,_,_,defs in added_reg_sets: # Do not need to care about default values - they will have 0 in the mask bits.
if 'FORCE_DFLT' in defs:
continue # do not use previous value, always use default value
if (op == 's') and (addr in self.initial_state): if (op == 's') and (addr in self.initial_state):
# old_data,old_mask=self.initial_state[addr]
old_data,_=self.initial_state[addr] old_data,_=self.initial_state[addr]
data=((old_data ^ data) & mask) ^ old_data data=((old_data ^ data) & mask) ^ old_data
# mask |= old_mask
# self.initial_state[addr]=(data,mask)
self.initial_state[addr]=(data,0) # ignoring old mask - only accumulating newly set bits in this set self.initial_state[addr]=(data,0) # ignoring old mask - only accumulating newly set bits in this set
def get_reg_names(self): def get_reg_names(self):
......
ezynq_uboot.py
View file @ 27df5bb0
...@@ -220,6 +220,15 @@ inline void pll_setup(void) ...@@ -220,6 +220,15 @@ inline void pll_setup(void)
self.cfile+='''/* Reset defined peripherals */ self.cfile+='''/* Reset defined peripherals */
inline void reset_peripherals(void) inline void reset_peripherals(void)
{ {
'''
self._add_reg_writes(reg_sets)
self.cfile+='}\n\n'
def gpio_out (self, reg_sets):
self.sections.append('gpio_out')
self.cfile+='''/* Setup GPIO outputs */
inline void setup_gpio_outputs(void)
{
''' '''
self._add_reg_writes(reg_sets) self._add_reg_writes(reg_sets)
self.cfile+='}\n\n' self.cfile+='}\n\n'
...@@ -499,9 +508,14 @@ int arch_cpu_init(void) ...@@ -499,9 +508,14 @@ int arch_cpu_init(void)
self.cfile+='\tuart_wait_tx_fifo_empty(); /* u-boot may re-program UART differently, wait all is sent before getting there */\n' self.cfile+='\tuart_wait_tx_fifo_empty(); /* u-boot may re-program UART differently, wait all is sent before getting there */\n'
#uart_wait_tx_fifo_empty() - add if u-boot debug is on #uart_wait_tx_fifo_empty() - add if u-boot debug is on
self._cp_led('LED_CHECKPOINT_12') # Before leaving lowlevel_init() self._cp_led('LED_CHECKPOINT_12') # Before leaving lowlevel_init()
#Setup GPIO outputs (after LED debug is over)
if 'gpio_out' in self.sections:
self.cfile+='\tsetup_gpio_outputs(); /* Setup GPIO outputs */\n'
#LOCK_SLCR #LOCK_SLCR
if self.features.get_par_value_or_none('LOCK_SLCR') is False: if self.features.get_par_value_or_none('LOCK_SLCR') is False:
self.cfile+='/* Leaving SLCR registers UNLOCKED according setting of %s */\n'%self.features.get_par_confname('LOCK_SLCR') self.cfile+='/* Leaving SLCR registers UNLOCKED according to setting of %s */\n'%self.features.get_par_confname('LOCK_SLCR')
else: else:
self.cfile+='''/* Lock SLCR back after everything with it is done */ self.cfile+='''/* Lock SLCR back after everything with it is done */
\tlock_slcr(); \tlock_slcr();
......
ezynqcfg.py
View file @ 27df5bb0
...@@ -448,6 +448,13 @@ if raw_config_value('CONFIG_EZYNQ_SKIP_DDR', raw_configs) is None: ...@@ -448,6 +448,13 @@ if raw_config_value('CONFIG_EZYNQ_SKIP_DDR', raw_configs) is None:
reg_sets=ddr.ddr_start(reg_sets,False,False) reg_sets=ddr.ddr_start(reg_sets,False,False)
segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'}) segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'})
#Set GPIO output pins
reg_sets=mio_regs.setregs_gpio(reg_sets)
segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'GPIO','TITLE':'GPIO outputs setup'})
# def setregs_gpio(self,current_reg_sets,force=True):
# Generate lock/unlock SLCR to be used in u-boot # Generate lock/unlock SLCR to be used in u-boot
reg_sets_lock_unlock=clk.generate_lock_unlock() reg_sets_lock_unlock=clk.generate_lock_unlock()
#print reg_sets[len(reg_sets)-1] #print reg_sets[len(reg_sets)-1]
...@@ -466,6 +473,7 @@ segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDRC_STA','TITLE':'regis ...@@ -466,6 +473,7 @@ segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDRC_STA','TITLE':'regis
# def generate_led_off_on(self, mio_pin): # def generate_led_off_on(self, mio_pin):
#CONFIG_EZYNQ_LED_DEBUG=47 # toggle LED during boot #CONFIG_EZYNQ_LED_DEBUG=47 # toggle LED during boot
#CONFIG_EZYNQ_BOOT_DEBUG #CONFIG_EZYNQ_BOOT_DEBUG
...@@ -493,6 +501,9 @@ if html_file: ...@@ -493,6 +501,9 @@ if html_file:
for segment in segments: for segment in segments:
start=segment['FROM'] start=segment['FROM']
end=segment['TO'] end=segment['TO']
# print segment['NAME'],start,end
if (start==end):
continue # nothing in this section
show_bit_fields= (MIO_HTML_MASK & 0x100,MIO_HTML_MASK & 0x800)[segment['NAME']=='MIO'] show_bit_fields= (MIO_HTML_MASK & 0x100,MIO_HTML_MASK & 0x800)[segment['NAME']=='MIO']
show_comments= MIO_HTML_MASK & 0x200 show_comments= MIO_HTML_MASK & 0x200
filter_fields=not MIO_HTML_MASK & 0x400 filter_fields=not MIO_HTML_MASK & 0x400
...@@ -573,6 +584,10 @@ if (args.lowlevel): ...@@ -573,6 +584,10 @@ if (args.lowlevel):
u_boot.ddr_start (reg_sets[segment_dict['DDR_START']['FROM']:segment_dict['DDR_START']['TO']]) u_boot.ddr_start (reg_sets[segment_dict['DDR_START']['FROM']:segment_dict['DDR_START']['TO']])
if 'DDRC_STA' in segment_dict: if 'DDRC_STA' in segment_dict:
u_boot.ddrc_wait_empty_queue(reg_sets[segment_dict['DDRC_STA']['FROM']:segment_dict['DDRC_STA']['TO']]) u_boot.ddrc_wait_empty_queue(reg_sets[segment_dict['DDRC_STA']['FROM']:segment_dict['DDRC_STA']['TO']])
if ('GPIO' in segment_dict) and (segment_dict['GPIO']['TO']>segment_dict['GPIO']['FROM']):
u_boot.gpio_out(reg_sets[segment_dict['GPIO']['FROM']:segment_dict['GPIO']['TO']])
#segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'GPIO','TITLE':'GPIO outputs setup'})
u_boot.make_arch_cpu_init() u_boot.make_arch_cpu_init()
u_boot.output_c_file(args.lowlevel) u_boot.output_c_file(args.lowlevel)
......
test.mk
View file @ 27df5bb0
...@@ -119,6 +119,10 @@ CONFIG_EZYNQ_MIO_UART_1=48 # 8+4*N ...@@ -119,6 +119,10 @@ CONFIG_EZYNQ_MIO_UART_1=48 # 8+4*N
#CONFIG_EZYNQ_MIO_GPIO_OUT_15= 1 # Set selected GPIO output to 0/1 #CONFIG_EZYNQ_MIO_GPIO_OUT_15= 1 # Set selected GPIO output to 0/1
## Boot image parameters ## Boot image parameters
#CONFIG_EZYNQ_MIO_INOUT_7= OUT # 'IN', 'BIDIR'
CONFIG_EZYNQ_MIO_GPIO_OUT_7= 1 # Set selected GPIO output to 0/1
#RBL header parameters #RBL header parameters
CONFIG_EZYNQ_BOOT_USERDEF= 0x1234567 # will be saved in the file header CONFIG_EZYNQ_BOOT_USERDEF= 0x1234567 # will be saved in the file header
......
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