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Commit 184bf0fb authored by Andrey Filippov's avatar Andrey Filippov
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u-boot-tree/arch/arm/cpu/armv7/zynq/Makefile 0 → 100644
View file @ 184bf0fb
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-y := timer.o
COBJS-y += cpu.o
COBJS-y += ddrc.o
COBJS-y += slcr.o
ifneq ($(CONFIG_EZYNQ),)
COBJS-y += lowlevel.o
endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
u-boot-tree/arch/arm/cpu/armv7/zynq/cpu.c 0 → 100644
View file @ 184bf0fb
/*
* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#ifndef CONFIG_EZYNQ
void lowlevel_init(void)
{
zynq_slcr_unlock();
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
/* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
writel(0x1F, &slcr_base->ocm_cfg);
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
writel(0x0, &slcr_base->fpga_rst_ctrl);
/* TZ_DDR_RAM, Set DDR trust zone non-secure */
writel(0xFFFFFFFF, &slcr_base->trust_zone);
/* Set urgent bits with register */
writel(0x0, &slcr_base->ddr_urgent_sel);
/* Urgent write, ports S2/S3 */
writel(0xC, &slcr_base->ddr_urgent);
zynq_slcr_lock();
}
#endif
void reset_cpu(ulong addr)
{
zynq_slcr_cpu_reset();
while (1)
;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif
u-boot-tree/boards.cfg 0 → 100644
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u-boot-tree/include/configs/ezynq/ezynq_MT41K256M16RE125.h 0 → 100644
View file @ 184bf0fb
/*
* (C) Copyright 2013 Elphel, Inc.
*
* Configuration for ezynq for Micron MT41K256M16RE125 DDR3L memory
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_EZYNQ_MT41K256M16RE125_H
#define __CONFIG_EZYNQ_MT41K256M16RE125_H
#define CONFIG_EZYNQ_DDR_DS_PARTNO MT41K256M16RE125 /* Memory part number (currently not used - derive some parameters later) */
/* CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE will be redefined to DDR3 as Zynq is slow with DDR3 */
#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE DDR3L /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
#define CONFIG_EZYNQ_DDR_DS_BANK_ADDR_COUNT 3 /* Number of DDR banks */
#define CONFIG_EZYNQ_DDR_DS_ROW_ADDR_COUNT 15 /* Number of DDR Row Address bits */
#define CONFIG_EZYNQ_DDR_DS_COL_ADDR_COUNT 10 /* Number of DDR Column address bits */
#define CONFIG_EZYNQ_DDR_DS_DRAM_WIDTH 16 /* Memory chip bus width (not yet used) */
#define CONFIG_EZYNQ_DDR_DS_RCD 7 /* DESCRIPTION':'RAS to CAS delay (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_RCD 13.1 /* Activate to internal Read or Write (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RCD automatically */
#define CONFIG_EZYNQ_DDR_DS_RP 7 /* Row Precharge time (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_RP 13.1 /* Precharge command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RP automatically, */
#define CONFIG_EZYNQ_DDR_DS_T_RC 48.75/* Activate to Activate or Refresh command period (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_RAS_MIN 35.0 /* Minimal Row Active time (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_FAW 40.0 /* Minimal running window for 4 page activates (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_RFC 300.0 /* Minimal Refresh-to-Activate or Refresh command period (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_WR 15.0 /* Write recovery time (ns) */
#define CONFIG_EZYNQ_DDR_DS_T_REFI_US 7.8 /* Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected */
#define CONFIG_EZYNQ_DDR_DS_RTP 4 /* Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK */
#define CONFIG_EZYNQ_DDR_DS_T_RTP 7.5 /* Minimal Read-to-Precharge time (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP */
#define CONFIG_EZYNQ_DDR_DS_WTR 4 /* Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK */
#define CONFIG_EZYNQ_DDR_DS_T_WTR 7.5 /* Minimal Write-to-Read time (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR */
#define CONFIG_EZYNQ_DDR_DS_XP 4 /* Minimal time from power down (DLL on) to any operation (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX 5.5 /* LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2 */
#define CONFIG_EZYNQ_DDR_DS_CCD 5 /* DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS) */
#define CONFIG_EZYNQ_DDR_DS_RRD 6 /* ACTIVATE-to-ACTIVATE minimal command period (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_RRD 10.0 /* ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically */
#define CONFIG_EZYNQ_DDR_DS_MRD 4 /* MODE REGISTER SET command period (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_MOD 12 /* MODE REGISTER SET update delay (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_MOD 15.0 /* MODE REGISTER SET update delay (ns). */
#define CONFIG_EZYNQ_DDR_DS_T_WLMRD 40.0 /* Write leveling : time to the first DQS rising edge (ns). */
#define CONFIG_EZYNQ_DDR_DS_CKE 3 /* CKE min pulse width (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_CKE 7.5 /* CKE min pulse width (ns). 5.625 */
#define CONFIG_EZYNQ_DDR_DS_CKSRE 5 /* Keep valid clock after self refresh/power down entry (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_CKSRE 10.0 /* Keep valid clock after self refresh/power down entry (ns). */
#define CONFIG_EZYNQ_DDR_DS_CKSRX 5 /* Valid clock before self refresh, power down or reset exit (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_T_CKSRX 10.0 /* Valid clock before self refresh, power down or reset exit (ns). */
#define CONFIG_EZYNQ_DDR_DS_ZQCS 64 /* ZQCS command: short calibration time (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_ZQCL 512 /* ZQCL command: long calibration time, including init (in tCK) */
#define CONFIG_EZYNQ_DDR_DS_INIT2 5 /* LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high */
#define CONFIG_EZYNQ_DDR_DS_T_INIT4_US 1.0 /* LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET command. */
#define CONFIG_EZYNQ_DDR_DS_T_INIT5_US 10.0 /* LPDDR2 only: tINIT5 (in us)- maximal duration of device auto initialization. */
#define CONFIG_EZYNQ_DDR_DS_T_ZQINIT_US 1.0 /* LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time. */
#endif /* __CONFIG_EZYNQ_MT41K256M16RE125_H */
u-boot-tree/include/configs/ezynq/ezynq_XC7Z010_1CLG400.h 0 → 100644
View file @ 184bf0fb
/*
* (C) Copyright 2013 Elphel, Inc.
*
* Configuration for ezynq for Xilinx XC7Z010_1CLG400 SoC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_XC7Z010_1CLG400_H
#define __CONFIG_XC7Z010_1CLG400_H
/* datasheet data for specific speed grades */
#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ 1600.0 /* Maximal PLL clock frequency for speed grade 1 (MHz) */
#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ 1800.0 /* Maximal PLL clock frequency for speed grade 2 (MHz) */
#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ 2000.0 /* Maximal PLL clock frequency for speed grade 3 (MHz) */
#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ 667.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ 733.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ 1000.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ 533.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ 600.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz */
#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ 710.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz */
#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS 1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS 1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS 1333.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
#define CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS 800.0 /* Maximal DDR3L, DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades */
#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ 355.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 1 */
#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ 408.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 2 */
#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ 444.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 3 */
/* SoC parameters to set phases manually (or as a starting point for automatic) Not yet processed */
#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0 0.0
#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1 0.0
#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2 0.0
#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3 0.0
#define CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH 504
#define CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH 495
#define CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH 520
#define CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH 835
#define CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH 465
#define CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH 480
#define CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH 550
#define CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH 780
#define CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH 470.0
#define CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH 470.0
#define CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH 470.0
#define CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH 470.0
/* Sorry for propOgation - this is how it is called in the tools */
#define CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY 160
#define CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY 160
#endif /* __CONFIG_XC7Z010_1CLG400_H */
u-boot-tree/include/configs/ezynq/zed_ezynq.h 0 → 100644
View file @ 184bf0fb
/*
* (C) Copyright 2013 Elphel, Inc.
*
* Configuration for Microzed RBL header
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 3 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_EZYNQ_H
#define __CONFIG_EZYNQ_H
#define CONFIG_EZYNQ
/* Boot image cionfiguration parameters */
#define CONFIG_EZYNQ_BOOT_USERDEF 0x1010000 /* 0x1234567 will be saved in the file header */
#define CONFIG_EZYNQ_BOOT_OCM_OFFSET 0x8c0 /* 0xa40 0x8C0 start of OCM data relative to the flash image start > 0x8C0, 63-bytes aligned */
#define CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH 0x30000 /* 0x1400c 0x30000 number of bytes to load to the OCM memory, < 0x30000 */
#define CONFIG_EZYNQ_START_EXEC 0x00 /* start of execution address */
#define CONFIG_EZYNQ_RESERVED44 0 /* documented as 0, but actually 1 */
/* Boot debug setup */
#define CONFIG_EZYNQ_BOOT_DEBUG /* configure UARTx and send register dumps there.*/
#define CONFIG_EZYNQ_LED_DEBUG 47 /* toggle LED during boot */
#define CONFIG_EZYNQ_UART_DEBUG_USE_LED /* turn on/off LED while waiting for transmit FIFO not full */
#define CONFIG_EZYNQ_DUMP_SLCR_EARLY /* Dump SLCR registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
#define CONFIG_EZYNQ_DUMP_DDRC_EARLY /* Dump DDRC registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
#define CONFIG_EZYNQ_DUMP_SLCR_LATE /* Dump SLCR registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
#define CONFIG_EZYNQ_DUMP_DDRC_LATE /* Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
/* Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG and CONFIG_EZYNQ_BOOT_DEBUG to be set
If defined, each can be 0,1, ON or OFF */
#define CONFIG_EZYNQ_LED_CHECKPOINT_1 ON /* in RBL setup, as soon as MIO is programmed */
#define CONFIG_EZYNQ_LED_CHECKPOINT_2 OFF /* First after getting to user code */
#define CONFIG_EZYNQ_LED_CHECKPOINT_3 ON /* After setting clock registers */
#define CONFIG_EZYNQ_LED_CHECKPOINT_4 OFF /* After PLL bypass is OFF */
#define CONFIG_EZYNQ_LED_CHECKPOINT_5 ON /* After UART is programmed */
#define CONFIG_EZYNQ_LED_CHECKPOINT_6 OFF /* After DCI is calibrated */
#define CONFIG_EZYNQ_LED_CHECKPOINT_7 ON /* After DDR is initialized */
#define CONFIG_EZYNQ_LED_CHECKPOINT_8 OFF /* Before relocation to DDR (to 0x4000000+ ) */
#define CONFIG_EZYNQ_LED_CHECKPOINT_9 ON /* After relocation to DDR (to 0x4000000+ ) */
#define CONFIG_EZYNQ_LED_CHECKPOINT_10 OFF /* Before remapping OCM0-OCM2 high */
#define CONFIG_EZYNQ_LED_CHECKPOINT_11 ON /* After remapping OCM0-OCM2 high */
#define CONFIG_EZYNQ_LED_CHECKPOINT_12 OFF /* Before leaving lowlevel_init() */
/* MIO configuration */
#define CONFIG_EZYNQ_OCM /* not used */
#define CONFIG_EZYNQ_MIO_0_VOLT 3.3
#define CONFIG_EZYNQ_MIO_1_VOLT 1.8
#define CONFIG_EZYNQ_QUADSPI_0__ATTRIB SLOW
#define CONFIG_EZYNQ_MIO_ETH_0__ATTRIB SLOW
#define CONFIG_EZYNQ_MIO_ETH_MDIO__ATTRIB SLOW
#define CONFIG_EZYNQ_MIO_USB_0__ATTRIB SLOW
#define CONFIG_EZYNQ_MIO_SDIO_0 40 // 16,28,40
#define CONFIG_EZYNQ_MIO_SDIO_0__ATTRIB SLOW
#define CONFIG_EZYNQ_MIO_SDCD_0 46 //#any but 7,8
#define CONFIG_EZYNQ_MIO_SDWP_0 50 //#any but 7,8
#define CONFIG_EZYNQ_MIO_UART_1 48 //# 8+4*N
/* LED will be OFF */
#define CONFIG_EZYNQ_MIO_INOUT_47 OUT
/*
Red LED - pullup, input - on,
output (or undefined) - off
#define CONFIG_EZYNQ_MIO_PULLUP_EN_47
#define CONFIG_EZYNQ_MIO_PULLUP_DIS_0
#define CONFIG_EZYNQ_MIO_INOUT_47 OUT
#define CONFIG_EZYNQ_MIO_INOUT_47 IN
#define CONFIG_EZYNQ_MIO_INOUT_47 BIDIR
*/
/* DDR chip independent */
#define CONFIG_EZYNQ_DDR_ENABLE Y /* Enable DDR memory */
/* Only specify CONFIG_EZYNQ_DDR_FREQ_MHZ if you want the DDR frequency used for timing calculations is different from actual */
/* #define CONFIG_EZYNQ_DDR_FREQ_MHZ 533.333333 */ /* DDR clock frequency in MHz, this value overwrites the one calculated by the PLL/clock setup */
#define CONFIG_EZYNQ_DDR_BANK_ADDR_MAP 10 /* DRAM address mapping: number of combined column and row addresses lower than BA0 */
#define CONFIG_EZYNQ_DDR_ARB_PAGE_BANK N /* Enable Arbiter prioritization based on page/bank match */
#define CONFIG_EZYNQ_DDR_ECC Disabled /* Enable ECC for the DDR memory */
#define CONFIG_EZYNQ_DDR_BUS_WIDTH 32 /* SoC DDR bus width */
#define CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL 0 /* Automatically train write leveling during initialization */
#define CONFIG_EZYNQ_DDR_TRAIN_READ_GATE 0 /* Automatically train read gate timing during initialization */
#define CONFIG_EZYNQ_DDR_TRAIN_DATA_EYE 0 /* Automatically train data eye during initialization */
#define CONFIG_EZYNQ_DDR_CLOCK_STOP_EN 0 /* Enable clock stop */
#define CONFIG_EZYNQ_DDR_USE_INTERNAL_VREF 0 /* Use internal Vref */
/* DDR chip Dependent */
#define CONFIG_EZYNQ_DDR_CL 7 /* CAS read latency (in tCK) */
#define CONFIG_EZYNQ_DDR_CWL 6 /* CAS write latency (in tCK) */
#define CONFIG_EZYNQ_DDR_AL 0 /* Posted CAS additive latency (in tCK) */
#define CONFIG_EZYNQ_DDR_BL 8 /* Burst length, 16 is only supported for LPDDR2 */
#define CONFIG_EZYNQ_DDR_HIGH_TEMP False /* Normal High temperature (influences refresh) */
#define CONFIG_EZYNQ_DDR_SPEED_BIN DDR3_1066F /* Memory speed bin (currently not used - derive timing later) */
#define CONFIG_EZYNQ_DDR_DDR2_RTT 75 /* DDR2 on-chip termination, Ohm ('DISABLED','75','150','50' */
#define CONFIG_EZYNQ_DDR_DDR3_RTT 60 /* DDR3 on-chip termination, Ohm ('DISABLED','60','120','40') Does not include 20 & 30 - not clear if DDRC can use them with auto write leveling */
#define CONFIG_EZYNQ_DDR_OUT_SLEW_NEG 26 /* Slew rate negative for DDR address/clock outputs */
#define CONFIG_EZYNQ_DDR_OUT_SLEW_POS 26 /* Slew rate positive for DDR address/clock outputs */
#define CONFIG_EZYNQ_DDR_OUT_DRIVE_NEG 12 /* Drive strength negative for DDR address/clock outputs */
#define CONFIG_EZYNQ_DDR_OUT_DRIVE_POS 28 /* Drive strength positive for DDR address/clock outputs */
#define CONFIG_EZYNQ_DDR_BIDIR_SLEW_NEG 31 /* Slew rate negative for driving DDR DQ/DQS signals */
#define CONFIG_EZYNQ_DDR_BIDIR_SLEW_POS 6 /* Drive strength positive for driving DDR DQ/DQS signals */
#define CONFIG_EZYNQ_DDR_BIDIR_DRIVE_NEG 12 /* Drive strength negative for driving DDR DQ/DQS signals */
#define CONFIG_EZYNQ_DDR_BIDIR_DRIVE_POS 28 /* Slew rate positive for driving DDR DQ/DQS signals */
/* Main clock settings */
#define CONFIG_EZYNQ_CLK_PS_MHZ 33.333333 /* PS_CLK System clock input frequency (MHz) */
#define CONFIG_EZYNQ_CLK_DDR_MHZ 533.333333 /* DDR clock frequency - DDR_3X (MHz) */
#define CONFIG_EZYNQ_CLK_ARM_MHZ 667 /* ARM CPU clock frequency cpu_6x4x (MHz) */
#define CONFIG_EZYNQ_CLK_CPU_MODE 6_2_1 /* CPU clocks set 6:2:1 (6:3:2:1) or 4:2:1 (4:2:2:1) */
#define CONFIG_EZYNQ_CLK_FPGA0_MHZ 50.0 /* FPGA 0 clock frequency (MHz) */
#define CONFIG_EZYNQ_CLK_FPGA1_MHZ 50.0 /* FPGA 1 clock frequency (MHz) */
#define CONFIG_EZYNQ_CLK_FPGA2_MHZ 50.0 /* FPGA 2 clock frequency (MHz) */
#define CONFIG_EZYNQ_CLK_FPGA3_MHZ 0.0 /* FPGA 3 clock frequency (MHz) */
#define CONFIG_EZYNQ_CLK_FPGA0_SRC IO /* FPGA 0 clock source */
#define CONFIG_EZYNQ_CLK_FPGA1_SRC IO /* FPGA 1 clock source */
#define CONFIG_EZYNQ_CLK_FPGA2_SRC None /* FPGA 2 clock source */
#define CONFIG_EZYNQ_CLK_FPGA3_SRC IO /* FPGA 3 clock source */
/* Normally do not need to be modified */
#define CONFIG_EZYNQ_CLK_DDR_DCI_MHZ 10.0 /* DDR DCI clock frequency (MHz). Normally 10 Mhz */
#define CONFIG_EZYNQ_CLK_DDR2X_MHZ 355.556 /* DDR2X clock frequency (MHz). Does not need to be exactly 2/3 of DDR3X clock */
#define CONFIG_EZYNQ_CLK_DDR_DCI_MHZ 10.0 /* DDR DCI clock frequency (MHz). Normally 10Mhz */
#define CONFIG_EZYNQ_CLK_SMC_MHZ 100.0 /* Static memory controller clock frequency (MHz). Normally 100 Mhz */
#define CONFIG_EZYNQ_CLK_QSPI_MHZ 200.0 /* Quad SPI memory controller clock frequency (MHz). Normally 200 Mhz */
#define CONFIG_EZYNQ_CLK_GIGE0_MHZ 125.0 /* GigE 0 Ethernet controller reference clock frequency (MHz). Normally 125 Mhz */
#define CONFIG_EZYNQ_CLK_GIGE1_MHZ 125.0 /* GigE 1 Ethernet controller reference clock frequency (MHz). Normally 125 Mhz */
#define CONFIG_EZYNQ_CLK_SDIO_MHZ 100.0 /* SDIO controller reference clock frequency (MHz). Normally 100 Mhz */
#define CONFIG_EZYNQ_CLK_UART_MHZ 25.0 /* UART controller reference clock frequency (MHz). Normally 25 Mhz */
#define CONFIG_EZYNQ_CLK_SPI_MHZ 200.0 /* SPI controller reference clock frequency (MHz). Normally 200 Mhz */
#define CONFIG_EZYNQ_CLK_CAN_MHZ 100.0 /* CAN controller reference clock frequency (MHz). Normally 100 Mhz */
#define CONFIG_EZYNQ_CLK_PCAP_MHZ 200.0 /* PCAP clock frequency (MHz). Normally 200 Mhz */
#define CONFIG_EZYNQ_CLK_TRACE_MHZ 100.0 /* Trace Port clock frequency (MHz). Normally 100 Mhz */
#define CONFIG_EZYNQ_CLK_ARM_SRC ARM /* ARM CPU clock source (normally ARM PLL) */
#define CONFIG_EZYNQ_CLK_DDR_SRC DDR /* DDR (DDR2x, DDR3x) clock source (normally DDR PLL) */
#define CONFIG_EZYNQ_CLK_DDR_DCI_SRC DDR /* DDR DCI clock source (normally DDR PLL) */
#define CONFIG_EZYNQ_CLK_SMC_SRC IO /* Static memory controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_QSPI_SRC ARM /* Quad SPI memory controller clock source (normally ARM PLL) */
#define CONFIG_EZYNQ_CLK_GIGE0_SRC IO /* GigE 0 Ethernet controller clock source (normally IO PLL, can be EMIO) */
#define CONFIG_EZYNQ_CLK_GIGE1_SRC IO /* GigE 1 Ethernet controller clock source (normally IO PLL, can be EMIO) */
#define CONFIG_EZYNQ_CLK_SDIO_SRC IO /* SDIO controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_UART_SRC IO /* UART controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_SPI_SRC IO /* SPI controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_CAN_SRC IO /* CAN controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_PCAP_SRC IO /* PCAP controller clock source (normally IO PLL) */
#define CONFIG_EZYNQ_CLK_TRACE_SRC IO /* Trace Port clock source (normally IO PLL) */
/* Even if memory itself is DDR3L (1.35V) it also can support DDR3 mode (1.5V). And unfortunately Zynq has degraded
specs at 1.35V (only 400MHz maximal clock), so datasheets's 'DDR3L' should be replaced with 'DDR3' and the board
power supply should be 1.5V - in that case 533MHz clock is possible */
#undef CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE
#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE DDR3 /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
/* performance data, final values (overwrite calculated) */
#define CONFIG_EZYNQ_CLK_SPEED_GRADE 3 /* Device speed grade */
/* #define CONFIG_EZYNQ_CLK_PLL_MAX_MHZ 1800.0 */ /* Maximal PLL clock frequency, MHz. Overwrites default for selected speed grade: (Speed grade -1:1600, -2:1800, -3:2000) */
/* #define CONFIG_EZYNQ_CLK_PLL_MIN_MHZ 780.0 */ /* Minimal PLL clock frequency, all speed grades (MHz) */
/* #define CONFIG_EZYNQ_CLK_ARM621_MAX_MHZ 733.0 */ /* Maximal ARM clk_6x4x in 621 mode, MHz. Overwrites default for selected speed grade: (Speed grade -1:667, -2:733, -3:1000) */
/* #define CONFIG_EZYNQ_CLK_ARM421_MAX_MHZ 600.0 */ /* Maximal ARM clk_6x4x in 421 mode, MHz. Overwrites default for selected speed grade: (Speed grade -1:533, -2:600, -3:710) */
/* #define CONFIG_EZYNQ_CLK_DDR_3X_MAX_MHZ 533.0 */ /* Maximal DDR clk_3x clock frequency (MHz). Overwrites DDR-type/speed grade specific */
/* #define CONFIG_EZYNQ_CLK_DDR_2X_MAX_MHZ 408.0 */ /* Maximal DDR_2X clock frequency (MHz). Overwrites speed grade specific */
#define CONFIG_EZYNQ_CLK_COMPLIANCE_PERCENT 5.0 /* Allow exceeding maximal limits by this margin (percent */
/* Board PCB layout parameters (not yet used) */
#define CONFIG_EZYNQ_DDR_BOARD_DELAY0 0.0
#define CONFIG_EZYNQ_DDR_BOARD_DELAY1 0.0
#define CONFIG_EZYNQ_DDR_BOARD_DELAY2 0.0
#define CONFIG_EZYNQ_DDR_BOARD_DELAY3 0.0
#define CONFIG_EZYNQ_DDR_DQS_0_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQS_1_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQS_2_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQS_3_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQ_0_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQ_1_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQ_2_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_DQ_3_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_CLOCK_0_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_CLOCK_1_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_CLOCK_2_LENGTH_MM 0
#define CONFIG_EZYNQ_DDR_CLOCK_3_LENGTH_MM 0
/* not yet processed
#define CONFIG_EZYNQ_DDR_PERIPHERAL_CLKSRC DDR PLL
#define CONFIG_EZYNQ_DDR_RAM_BASEADDR 0x00100000
#define CONFIG_EZYNQ_DDR_RAM_HIGHADDR 0x3FFFFFFF
*/
#endif /* __CONFIG_EZYNQ_H */
u-boot-tree/include/configs/zynq_microzed.h 0 → 100644
View file @ 184bf0fb
/*
* (C) Copyright 2012 Xilinx
*
* Configuration for Zynq Evaluation and Development Board - ZedBoard
* See zynq_common.h for Zynq common configs
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_ZYNQ_MICROZED_H
#define __CONFIG_ZYNQ_MICROZED_H
/*#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) */
#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
#if 0
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#endif
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0
//#define CONFIG_ZYNQ_SPI
//#define CONFIG_NAND_ZYNQ
#undef CONFIG_SYS_TEXT_BASE
#include <configs/zynq_common.h>
#include <configs/ezynq/ezynq_MT41K256M16RE125.h> /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
#include <configs/ezynq/ezynq_XC7Z010_1CLG400.h>
#include <configs/ezynq/zed_ezynq.h>
/* twice slower */
#undef CONFIG_ZYNQ_SERIAL_CLOCK0
/*#define CONFIG_ZYNQ_SERIAL_CLOCK0 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK0 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_ZYNQ_SERIAL_CLOCK1
/*#define CONFIG_ZYNQ_SERIAL_CLOCK1 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK1 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_BOOTDELAY
#undef CONFIG_SYS_PROMPT
#undef CONFIG_SYS_SDRAM_BASE
#undef CONFIG_ENV_SIZE
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_BOOTDELAY -1 /* -1 to Disable autoboot */
#define CONFIG_SYS_PROMPT "ezynq> "
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Physical start address of SDRAM. _Must_ be 0 here. */
#define CONFIG_ENV_SIZE 1400
#if 0
#define CONFIG_SYS_TEXT_BASE 0x04000000 /*with 0x04000000 - does not get to the low_Level_init? */
#else
#define CONFIG_SYS_TEXT_BASE 0x00000000 //0x04000000 with 0x04000000 - does not get to the low_Level_init?
#endif
/*
#define CONFIG_EZYNQ_SKIP_DDR
*/
#define CONFIG_EZYNQ_SKIP_CLK
//undefs
/* undefs */
/*#undef CONFIG_FS_FAT */
#undef CONFIG_SUPPORT_VFAT
#undef CONFIG_CMD_FAT
/* http://lists.denx.de/pipermail/u-boot/2003-October/002631.html */
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
/* CONFIG_FS_FAT=y */
/* disable PL*/
#undef CONFIG_FPGA
#undef CONFIG_FPGA_XILINX
#undef CONFIG_FPGA_ZYNQPL
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_EXT2
#undef CONFIG_CMD_CACHE
#undef DEBUG
/* redefine env settings*/
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"ethaddr=00:0a:35:00:01:22\0" \
"kernel_image=uImage\0" \
"ramdisk_image=uramdisk.image.gz\0" \
"devicetree_image=devicetree.dtb\0" \
"bitstream_image=system.bit.bin\0" \
"loadbit_addr=0x100000\0" \
"kernel_size=0x500000\0" \
"devicetree_size=0x20000\0" \
"ramdisk_size=0x5E0000\0" \
"fdt_high=0x20000000\0" \
"initrd_high=0x20000000\0" \
"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
"mmcinfo && " \
"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
"fpga load 0 ${loadbit_addr} ${filesize}\0" \
"sdboot=echo Copying Linux from SD to RAM... && " \
"mmcinfo && " \
"fatload mmc 0 0x3000000 ${kernel_image} && " \
"fatload mmc 0 0x2A00000 ${devicetree_image} && " \
"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"nandboot=echo Copying Linux from NAND flash to RAM... && " \
"nand read 0x3000000 0x100000 ${kernel_size} && " \
"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
"echo Copying ramdisk... && " \
"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0"
/* */
#endif /* __CONFIG_ZYNQ_MICROZED_H */
u-boot-tree/makeuboot 0 → 100755
View file @ 184bf0fb
#!/bin/bash
export CROSS_COMPILE=arm-poky-linux-gnueabi-
export PATH=/opt/poky/1.4/sysroots/x86_64-pokysdk-linux/usr/bin/armv7a-vfp-neon-poky-linux-gnueabi/:$PATH
make clean
make zynq_microzed_config
make include/autoconf.mk
ezynq/ezynqcfg.py -c include/autoconf.mk --html u-boot.html -o boot_head.bin --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/lowlevel.c
make
cat boot_head.bin u-boot.bin > boot.bin
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