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ezynq
Commit 0876f70c authored by Andrey Filippov's avatar Andrey Filippov
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Moved the original MIO setup code to a separate file/class

parent c897608a
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Showing with 297 additions and 800 deletions
.gitignore
View file @ 0876f70c
*.pyc
*.hex
*.bin
*.gz
*.html
*.log
*~
ezynq_ddr.py
View file @ 0876f70c
......@@ -41,28 +41,34 @@ class EzynqDDR:
self.DDRC_DEFS= ezynq_ddrc_defs.DDRC_DEFS
self.DDRIOB_DEFS=ezynq_ddriob_def.DDRIOB_DEFS
self.DDR_CFG_DEFS=ezynq_ddrcfg_defs.DDR_CFG_DEFS
self.ddrc_register_sets= {'PRE': ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits), # all now start from the same registers
'MAIN':ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits),
'POST':ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits)}
self.ddriob_register_sets= {'PRE': ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits), # all now start from the same registers
'MAIN':ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits),
'POST':ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits)}
# self.set_names=('PRE','MAIN','POST')
self.set_ddrc_attribs=(
{'NAME':'PRE','POSTFIX':'_PRE','PREFIX':'CONFIG_EZYNQ_DDR_SETREG_','TITLE':"DDR Controller Register Pre-Set"},
{'NAME':'MAIN','POSTFIX':'','PREFIX':'CONFIG_EZYNQ_DDR_SETREG_','TITLE':"DDR Controller Register Set"},
{'NAME':'POST','POSTFIX':'_POST','PREFIX':'CONFIG_EZYNQ_DDR_SETREG_','TITLE':"DDR Controller Register Post-Set"})
self.set_ddiob_attribs=(
{'NAME':'PRE','POSTFIX':'_PRE','PREFIX':'CONFIG_EZYNQ_DDRIOB_SETREG_','TITLE':"DDR I/O Buffer Register Pre-Set"},
{'NAME':'MAIN','POSTFIX':'','PREFIX':'CONFIG_EZYNQ_DDRIOB_SETREG_','TITLE':"DDR I/O Buffer Register Set"},
{'NAME':'POST','POSTFIX':'_POST','PREFIX':'CONFIG_EZYNQ_DDRIOB_SETREG_','TITLE':"DDR I/O Buffer Register Post-Set"})
self.postfixes=[attrib['POSTFIX'] for attrib in self.set_ddrc_attribs]
# self.ddrc_register_sets= {'PRE': ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits), # all now start from the same registers
# 'MAIN':ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits),
# 'POST':ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits)}
# self.ddriob_register_sets= {'PRE': ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits), # all now start from the same registers
# 'MAIN':ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits),
# 'POST':ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits)}
# self.set_ddrc_attribs=(
# {'NAME':'PRE','POSTFIX':'_PRE','PREFIX':'CONFIG_EZYNQ_DDR_SETREG_','TITLE':"DDR Controller Register Pre-Set"},
# {'NAME':'MAIN','POSTFIX':'','PREFIX':'CONFIG_EZYNQ_DDR_SETREG_','TITLE':"DDR Controller Register Set"},
# {'NAME':'POST','POSTFIX':'_POST','PREFIX':'CONFIG_EZYNQ_DDR_SETREG_','TITLE':"DDR Controller Register Post-Set"})
# self.set_ddiob_attribs=(
# {'NAME':'PRE','POSTFIX':'_PRE','PREFIX':'CONFIG_EZYNQ_DDRIOB_SETREG_','TITLE':"DDR I/O Buffer Register Pre-Set"},
# {'NAME':'MAIN','POSTFIX':'','PREFIX':'CONFIG_EZYNQ_DDRIOB_SETREG_','TITLE':"DDR I/O Buffer Register Set"},
# {'NAME':'POST','POSTFIX':'_POST','PREFIX':'CONFIG_EZYNQ_DDRIOB_SETREG_','TITLE':"DDR I/O Buffer Register Post-Set"})
# self.postfixes=[attrib['POSTFIX'] for attrib in self.set_ddrc_attribs]
self.features=ezynq_feature_config.EzynqFeatures(self.DDR_CFG_DEFS,0) #DDR_CFG_DEFS
self.ddrc_register_set= ezynq_registers.EzynqRegisters(self.DDRC_DEFS,0,regs_masked,permit_undefined_bits)
self.ddriob_register_set=ezynq_registers.EzynqRegisters(self.DDRIOB_DEFS,0,regs_masked,permit_undefined_bits)
def parse_parameters(self,raw_configs):
self.features.parse_features(raw_configs)
def check_missing_features(self):
self.features.check_missing_features()
def html_list_features(self,html_file):
if not html_file:
return
html_file.write('<h2>DDR memory configuration parameters</h2>\n')
self.features.html_list_features(html_file)
def calculate_dependent_pars(self):
......@@ -250,17 +256,20 @@ class EzynqDDR:
return (address_mapping,page_mask)
def get_new_register_sets(self):
return self.ddrc_register_sets['MAIN'].get_register_sets(True,True)
# return self.ddrc_register_sets['MAIN'].get_register_sets(True,True)
return self.ddrc_register_set.get_register_sets(True,True)
def ddr_init_memory(self,current_reg_sets,force=False,warn=False): # will program to sequence 'MAIN'
def ddr_init_memory(self,current_reg_sets,force=False,warn=False):
# print 'ddr_init_memory, len(current_reg_sets)=',len(current_reg_sets),'\n'
if not self.features.get_par_value('ENABLE'):
print 'DDR configuration is disabled'
# do some stuff (write regs, output)
return
ddriob_register_set=self.ddriob_register_sets['MAIN']
ddrc_register_set= self.ddrc_register_sets['MAIN']
# ddriob_register_set=self.ddriob_register_sets['MAIN']
# ddrc_register_set= self.ddrc_register_sets['MAIN']
ddriob_register_set=self.ddriob_register_set
ddrc_register_set= self.ddrc_register_set
ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
self.ddr_init_ddriob(force,warn) # will program to sequence 'MAIN'
......@@ -270,7 +279,8 @@ class EzynqDDR:
return ddrc_register_set.get_register_sets(True,True)
def ddr_init_ddrc(self,force=False,warn=False): # will program to sequence 'MAIN'
ddrc_register_set=self.ddrc_register_sets['MAIN']
# ddrc_register_set=self.ddrc_register_sets['MAIN']
ddrc_register_set=self.ddrc_register_set
is_LPDDR2= (self.features.get_par_value('MEMORY_TYPE')=='LPDDR2')
is_DDR3L= (self.features.get_par_value('MEMORY_TYPE')=='DDR3L')
is_DDR3_15= (self.features.get_par_value('MEMORY_TYPE')=='DDR3')
......@@ -1324,7 +1334,8 @@ class EzynqDDR:
def ddr_init_ddriob(self,force=False,warn=False): # will program to sequence 'MAIN'
# print 'ddr_init_ddriob\n'
ddriob_register_set=self.ddriob_register_sets['MAIN']
# ddriob_register_set=self.ddriob_register_sets['MAIN']
ddriob_register_set=self.ddriob_register_set
# DDRIOB configuration UG585.268
is_LPDDR2= (self.features.get_par_value('MEMORY_TYPE')=='LPDDR2')
is_DDR3L= (self.features.get_par_value('MEMORY_TYPE')=='DDR3L')
......@@ -1437,6 +1448,8 @@ class EzynqDDR:
('nref_opt4',1),
('pref_opt2',0),
('update_control',0)),force,warn)
#TODO: Remove?
def parse_ddrc_raw_register_set(self,raw_configs,qualifier_char,force=True,warn=True):
# for i,attribs in enumerate(self.set_attribs):
......@@ -1455,6 +1468,8 @@ class EzynqDDR:
postfix= attribs['POSTFIX']
reg_set.parse_options_set(raw_configs,prefix,postfix,self.postfixes,qualifier_char,force,warn) #force - readonly/undefined fields, warn: data does not fit in the bit field
def print_ddrc_html_registers(self, html_file, show_bit_fields=True, show_comments=True,filter_fields=True):
if not html_file:
return
for attribs in self.set_ddrc_attribs:
reg_set_name=attribs['NAME']
reg_set= self.ddrc_register_sets[reg_set_name]
......@@ -1463,6 +1478,8 @@ class EzynqDDR:
reg_set.print_html_registers(html_file, show_bit_fields, show_comments,filter_fields)
html_file.write('<br/>\n')
def print_ddriob_html_registers(self, html_file, show_bit_fields=True, show_comments=True,filter_fields=True):
if not html_file:
return
for attribs in self.set_ddrc_attribs:
reg_set_name=attribs['NAME']
reg_set= self.ddrc_register_sets[reg_set_name]
......
ezynq_feature_config.py
View file @ 0876f70c
......@@ -206,6 +206,8 @@ class EzynqFeatures:
def html_list_features(self,html_file):
if not html_file:
return
html_file.write('<table border="1">\n')
html_file.write('<tr><th>Configuration name</th><th>Value</th><th>Type/<br/>Choices</th><th>Mandatory</th><th>Origin</th><th>Default</th><th>Description</th></tr>\n')
# print self.get_par_names()
......
ezynq_registers.py
View file @ 0876f70c
......@@ -24,6 +24,8 @@ __status__ = "Development"
# new_sets.append((addr,data,mask,self.module_name,register_name,self.registers[register_name]))
def print_html_reg_header(html_file, title='',show_bit_fields=True, show_comments=True,filter_fields=True):
if not html_file:
return
if title:
html_file.write('<h2>'+title+'</h2>\n')
html_file.write('<table border="1">\n')
......@@ -35,9 +37,14 @@ def print_html_reg_header(html_file, title='',show_bit_fields=True, show_comment
html_file.write('<th>Comments</th>')
html_file.write('</tr>')
def print_html_reg_footer(html_file):
if not html_file:
return
html_file.write('</table>\n')
def print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comments=True,filter_fields=True):
if not html_file:
return
# new_sets.append((addr,data,mask,self.module_name,register_name,self.registers[register_name]))
current_reg_state={} #address: (data,mask)
for addr, data, mask, module_name, register_name, r_def in reg_sets:
......
ezynq_slcr_clk_def.py
View file @ 0876f70c
......@@ -25,8 +25,7 @@ __status__ = "Development"
SLCR_CLK_DEFS={ #not all fields are defined currently
'BASE_ADDR':(0xF8000000,), # SLCR
'MODULE_NAME':('slcr',),
'scl': {'OFFS': 0x000,'DFLT':0x0,'RW':'RW,
'scl': {'OFFS': 0x000,'DFLT':0x0,'RW':'RW',
'COMMENTS':'Secure configurqation lock (no way to unlock until POR)',
'FIELDS':{
'lock': {'r':(0,0),'d':0, 'c':'1 - lock (locker on R) write to scl,pss_rst,apu_ctrl,wdt_clk_sel'}}},
......@@ -95,7 +94,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
'FIELDS':{
'reserved1': {'r':(22,31),'d':0, 'c':'reserved'},
'lock_cnt': {'r':(12,21),'d':0x177, 'c':'Lock status bit delay (in clock cycles)'}, # reference or output clock cycles? 0xfa
'pll_cp': {'r':( 8:11),'d':0xe, 'c':'PLL charge pump control'}, # 0x2
'pll_cp': {'r':( 8,11),'d':0xe, 'c':'PLL charge pump control'}, # 0x2
'pll_res': {'r':( 4, 7),'d':0xa, 'c':'PLL loop filter resistor control'}, # 0x2
'reserved2': {'r':( 0, 3),'d':0, 'c':'reserved'}}},
......@@ -104,7 +103,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
'FIELDS':{
'reserved1': {'r':(22,31),'d':0, 'c':'reserved'},
'lock_cnt': {'r':(12,21),'d':0x177, 'c':'Lock status bit delay (in clock cycles)'}, # reference or output clock cycles? 0x12c
'pll_cp': {'r':( 8:11),'d':0xe, 'c':'PLL charge pump control'}, # 0x2
'pll_cp': {'r':( 8,11),'d':0xe, 'c':'PLL charge pump control'}, # 0x2
'pll_res': {'r':( 4, 7),'d':0xa, 'c':'PLL loop filter resistor control'}, # 0x2
'reserved2': {'r':( 0, 3),'d':0, 'c':'reserved'}}},
......@@ -113,7 +112,7 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
'FIELDS':{
'reserved1': {'r':(22,31),'d':0, 'c':'reserved'},
'lock_cnt': {'r':(12,21),'d':0x177, 'c':'Lock status bit delay (in clock cycles)'}, # reference or output clock cycles? 0x145
'pll_cp': {'r':( 8:11),'d':0xe, 'c':'PLL charge pump control'}, # 0x2
'pll_cp': {'r':( 8,11),'d':0xe, 'c':'PLL charge pump control'}, # 0x2
'pll_res': {'r':( 4, 7),'d':0xa, 'c':'PLL loop filter resistor control'}, # 0xc
'reserved2': {'r':( 0, 3),'d':0, 'c':'reserved'}}},
......@@ -600,7 +599,167 @@ SLCR_CLK_DEFS={ #not all fields are defined currently
'FIELDS':{
'reserved': {'r':( 1,31),'d':0, 'c':'reserved'},
'OCM_rst': {'r':( 0, 0),'d':0, 'c':'OCM subsystem reset: 0 - normal, 1 - reset'}}},
#next register set is OFFS=0x240
'fpga_rst_ctrl': {'OFFS': 0x240,'DFLT':0x01f33f0f,'RW':'RW', #0xffffffff->0x0
'COMMENTS':'FPGA software reset control',
'FIELDS':{
'reserved_3': {'r':(25,31),'d':0, 'c':'reserved'}, #0x7f->0x0
'fpga_acp_rst': {'r':(24,24),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_axds3_rst': {'r':(23,23),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_axds2_rst': {'r':(22,22),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_axds1_rst': {'r':(21,21),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_axds0_rst': {'r':(20,20),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'reserved_2': {'r':(18,19),'d':0, 'c':'reserved'}, #0x3 ->0x0
'fssw1_fpga_rst': {'r':(17,17),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fssw0_fpga_rst': {'r':(16,16),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'reserved_1': {'r':(14,15),'d':0, 'c':'reserved'}, #0x3 ->0x0
'fpga_fmsw1_rst': {'r':(13,13),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_fmsw0_rst': {'r':(12,12),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_dma3_rst': {'r':(11,11),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_dma2_rst': {'r':(10,10),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_dma1_rst': {'r':( 9, 9),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'fpga_dma0_rst': {'r':( 8, 8),'d':0x1, 'c':'reserved'}, #0x1 ->0x0
'reserved': {'r':( 4, 7),'d':0, 'c':'reserved'}, #0xf ->0x0
'fpga3_out_rst': {'r':( 3, 3),'d':0x1, 'c':'PL reset3 (FCLKRESETN3): 0 - deassert (logic high state), 1 - assert (logic low state)'}, #0x1 ->0x0
'fpga2_out_rst': {'r':( 2, 2),'d':0x1, 'c':'PL reset2 (FCLKRESETN2): 0 - deassert (logic high state), 1 - assert (logic low state)'}, #0x1 ->0x0
'fpga1_out_rst': {'r':( 1, 1),'d':0x1, 'c':'PL reset1 (FCLKRESETN1): 0 - deassert (logic high state), 1 - assert (logic low state)'}, #0x1 ->0x0
'fpga0_out_rst': {'r':( 0, 0),'d':0x1, 'c':'PL reset0 (FCLKRESETN0): 0 - deassert (logic high state), 1 - assert (logic low state)'}}}, #0x1 ->0x0
'a9_cpu_rst_ctrl': {'OFFS': 0x244,'DFLT':0,'RW':'RW', # Never set
'COMMENTS':'CPU reset and clock control',
'FIELDS':{
'reserved1': {'r':( 9,31),'d':0, 'c':'reserved'},
'peri_rst': {'r':( 8, 8),'d':0, 'c':'CPU peripheral soft reset (0 normal, 1 - hold in reset)'},
'reserved2': {'r':( 6, 7),'d':0, 'c':'reserved'},
'a9_clkstop1': {'r':( 5, 5),'d':0, 'c':'CPU 1 clock stop control: 0 - run, 1 - stop'},
'a9_clkstop0': {'r':( 4, 4),'d':0, 'c':'CPU 0 clock stop control: 0 - run, 1 - stop'},
'reserved3': {'r':( 3, 2),'d':0, 'c':'reserved'},
'a9_rst1': {'r':( 1, 1),'d':0, 'c':'CPU 1 software reset control: 0 - no reset, 1 - hold in reset'},
'a9_rst0': {'r':( 0, 0),'d':0, 'c':'CPU 0 software reset control: 0 - no reset, 1 - hold in reset'}}},
'ps_awdt_ctrl': {'OFFS': 0x24c,'DFLT':0,'RW':'RW', # Never set
'COMMENTS':'CPU reset and clock control',
'FIELDS':{
'reserved': {'r':( 2,31),'d':0, 'c':'reserved'},
'ctrl1': {'r':( 1, 1),'d':0, 'c':'Select target for APU watchdog timer 1: 0 - same as PS_SRST_B, 1 - CPU associated with this WDT'},
'ctrl0': {'r':( 0, 0),'d':0, 'c':'Select target for APU watchdog timer 0: 0 - same as PS_SRST_B, 1 - CPU associated with this WDT'}}},
'reboot_status': {'OFFS': 0x258,'DFLT':0x00400000,'RW':'RW', # Never set
'COMMENTS':'Reboot status, persistent through reboots (but POR)',
'FIELDS':{
'reboot_state': {'r':(24,31),'d':0, 'c':'1 byte data that is preserved through all resets but POR. RBL puts last known reset reason here'},
'reserved': {'r':(23,23),'d':0, 'c':'reserved'},
'por': {'r':(22,22),'d':0x1, 'c':'Last reset was POR (written by RBL)'},
'srst_b': {'r':(21,21),'d':0, 'c':'Last reset was SRST_B (written by RBL)'},
'dbg_rst': {'r':(20,20),'d':0, 'c':'Last reset was by debug system (written by RBL)'},
'slc_rst': {'r':(19,19),'d':0, 'c':'Last reset was SLC soft reset (written by RBL)'},
'awdt1_rst': {'r':(18,18),'d':0, 'c':'Last reset was by APU watchdog timer1 (written by RBL)'},
'awdt0_rst': {'r':(17,17),'d':0, 'c':'Last reset was by APU watchdog timer0 (written by RBL)'},
'swdt_rst': {'r':(16,16),'d':0, 'c':'Last reset was by system watchdog timeout (written by RBL)'},
'bootrom_error_code': {'r':( 0,15),'d':0, 'c':'RBL error code (written by RBL)'}}},
'boot_mode': {'OFFS': 0x25c,'RW':'M', #
'COMMENTS':'Boot mode strapping pins state',
'FIELDS':{
'reserved': {'r':( 5,31),'d':0, 'c':'reserved'},
'pll_bypass': {'r':( 4, 4),'d':0, 'm':'R', 'c':'1 PLL is enabled, outputs routed to clock generators, 0 - PLLs are diusabled and bypassed'},
'boot_mode': {'r':( 0, 3), 'm':'R', 'c':'boot mode pins as sampled'}}},
'apu_ctrl': {'OFFS': 0x300,'DFLT':0,'RW':'RW', # Never set
'COMMENTS':'APU control',
'FIELDS':{
'reserved': {'r':( 3,31),'d':0, 'c':'reserved'},
'cfgsdisable': {'r':( 2, 2),'d':0, 'c':'Disable write to some system control processor registers and some GIC registers. Reset by POR only'},
'cp15sdiasble': {'r':( 0, 1),'d':0, 'c':'Disable write to some system control processor (CP15) registers in each processor. Reset by POR only'}}},
'wdt_clk_sel': {'OFFS': 0x304,'DFLT':0,'RW':'RW', # Never set
'COMMENTS':'SWDT source clock select',
'FIELDS':{
'reserved': {'r':( 1,31),'d':0, 'c':'reserved'},
'sel': {'r':( 0, 1),'d':0, 'c':'SWDT clock select: 0 - internal CPU_1x, 1 - PL via EMIO or MIO pin'}}},
'ddr_urgent': {'OFFS': 0x600, 'DFLT':0,'RW':'RW',
'COMMENTS':'DDR Urgent Control',
'FIELDS':{
'reserved': {'r':( 8,31),'d':0, 'c':'reserved'},
's3_arurgent': {'r':( 7, 7),'d':0, 'c':'Read port 3 - set high priority'},
's2_arurgent': {'r':( 6, 6),'d':0, 'c':'Read port 2 - set high priority'},
's3_arurgent': {'r':( 5, 5),'d':0, 'c':'Read port 1 - set high priority'},
's0_arurgent': {'r':( 4, 4),'d':0, 'c':'Read port 0 - set high priority'},
's3_awurgent': {'r':( 3, 3),'d':0, 'c':'Write port 3 - set high priority'},
's2_awurgent': {'r':( 2, 2),'d':0, 'c':'Write port 2 - set high priority'},
's1_awurgent': {'r':( 1, 1),'d':0, 'c':'Write port 1 - set high priority'},
's0_awurgent': {'r':( 0, 0),'d':0, 'c':'Write port 0 - set high priority'}}},
'ddr_cal_start': {'OFFS': 0x60c,'DFLT':0,'RW':'RW',
'COMMENTS':'DDR Calibration start',
'FIELDS':{
'reserved': {'r':( 2,31),'d':0, 'c':'reserved'},
'start_cal_dll': {'r':( 1, 1),'d':0, 'c':'1 - Start DLL calibration command (self-clearing). Only needed if auto calibration is disabled in reg_ddrc_dis_dll_calib'},
'start_cal_short': {'r':( 0, 0),'d':0, 'c':'1 - Start ZQ calibration short command (self-clearing). Only needed if auto calibration is disabled in reg_ddrc_dis_auto_dq'}}},
'ddr_ref_start': {'OFFS': 0x614,'DFLT':0,'RW':'RW',
'COMMENTS':'DDR Refresh start',
'FIELDS':{
'reserved': {'r':( 1,31),'d':0, 'c':'reserved'},
'start_ref': {'r':( 0, 0),'d':0, 'c':'1 - Start Refresh (self-clearing). Only needed if auto refresh is disabled in reg_ddrc_dis_auto_refresh'}}},
'ddr_cmd_sta': {'OFFS': 0x618,'DFLT':0,'RO':'RW',
'COMMENTS':'DDR Command queue state',
'FIELDS':{
'reserved': {'r':( 1,31),'d':0, 'c':'reserved'},
'vmd_q_empty': {'r':( 0, 0),'d':0, 'm':'R', 'c':'0 - no commands fro DDRC are queued, 1 - commands pending'}}},
'ddr_urgent_sel': {'OFFS': 0x61c,'DFLT':0,'RW':'RW',
'COMMENTS':'DDR Urgent select',
'FIELDS':{
'reserved': {'r':(16,31),'d':0, 'c':'reserved'},
's3_ar_qos_mode': {'r':(14,15),'d':0, 'c':'Select DDRC s3_arurgent source: 0 - ddr_urgent_val reg. bit, 1 - s3_arqos bit, 2 - fabric ddr_arb[3]'},
's2_ar_qos_mode': {'r':(12,13),'d':0, 'c':'Select DDRC s2_arurgent source: 0 - ddr_urgent_val reg. bit, 1 - s2_arqos bit, 2 - fabric ddr_arb[2]'},
's1_ar_qos_mode': {'r':(10,11),'d':0, 'c':'Select DDRC s1_arurgent source: 0 - ddr_urgent_val reg. bit, 1 - s1_arqos bit, 2 - fabric ddr_arb[1]'},
's0_ar_qos_mode': {'r':( 8, 9),'d':0, 'c':'Select DDRC s0_arurgent source: 0 - ddr_urgent_val reg. bit, 2 - fabric ddr_arb[0]'},
's3_aw_qos_mode': {'r':( 6, 7),'d':0, 'c':'Select DDRC s3_awurgent source: 0 - ddr_urgent_val reg. bit, 1 - s3_awqos bit, 2 - fabric ddr_arb[3]'},
's2_aw_qos_mode': {'r':( 4, 5),'d':0, 'c':'Select DDRC s2_awurgent source: 0 - ddr_urgent_val reg. bit, 1 - s3_awqos bit, 2 - fabric ddr_arb[2]'},
's1_aw_qos_mode': {'r':( 2, 3),'d':0, 'c':'Select DDRC s1_awurgent source: 0 - ddr_urgent_val reg. bit, 1 - s3_awqos bit, 2 - fabric ddr_arb[1]'},
's0_aw_qos_mode': {'r':( 0, 1),'d':0, 'c':'Select DDRC s0_awurgent source: 0 - ddr_urgent_val reg. bit, 2 - fabric ddr_arb[0]'}}},
'ddr_dfi_status': {'OFFS': 0x620,'RW':'M', #
'COMMENTS':'DDR DFI status',
'FIELDS':{
'reserved': {'r':( 1,31),'d':0, 'c':'reserved'},
'dfi_cal_st': {'r':( 0, 3),'d':0,'m':'R', 'c':'Not clear'}}},
}
MIO_PINS_DEFS={'mio_pin_%02i'%i:{'OFFS': 0x700+4*i,
'DFLT':0x1601,
'RW':'RW',
'COMMENTS':'MIO pin %i control'%i,
'FIELDS':{
'reserved': {'r':(14,31),'d':0, 'c':'reserved'},
'disable_rcv': {'r':(13,13),'d':0, 'c':'disable HSTL input buffer'},
'pullup': {'r':(12,12),'d':0x1, 'c':'1 - enable pullup, 0 - disable'},
'io_type': {'r':( 9,11),'d':0x3, 'c':'1 - LVCMOS18,2 - LVCMOS25,3 -LVCMOS33, 4 - HSTL'},
'fast': {'r':( 8, 8),'d':0, 'c':'Output driver edge rate:1 - fast, 0 - slow'},
'l3_sel': {'r':( 5, 7),'d':0, 'c':'level 3 mux select'},
'l2_sel': {'r':( 3, 4),'d':0, 'c':'level 2 mux select'},
'l1_sel': {'r':( 2, 2),'d':0, 'c':'level 1 mux select'},
'l0_sel': {'r':( 1, 1),'d':0, 'c':'level 0 mux select'},
'tri_enable': {'r':( 0, 0),'d':1, 'c':'1 - enable tri-state, 0 - disable'}}}
for i in range (54)}
MIO_PINS_DEFS['BASE_ADDR']=(0xF8000000,) # SLCR
MIO_PINS_DEFS['MODULE_NAME']=('slcr',)
#UG585: table 25-6: multiplier (PLL_FDIV), PLL_CP, PLL_RES, LOCK_CNT
PLL_PARS=(( 13, 2,6,750),
( 14, 2,6,700),
( 15, 2,6,650),
( 16, 2,10,625),
( 17, 2,10,575),
( 18, 2,10,550),
( 19, 2,10,525),
( 20, 2,12,500),
( 21, 2,12,475),
( 22, 2,12,450),
( 23, 2,12,425),
((24,25),2,12,400),
( 26, 2,12,375),
((27,28),2,12,350),
((29,30),2,12,325),
((31,33),2,12,300),
((34,36),2,12,275),
((37,40),2,12,250),
((41,47),3,12,250),
((48,66),3,12,250))
\ No newline at end of file
ezynqcfg.py
View file @ 0876f70c
......@@ -24,7 +24,7 @@ __status__ = "Development"
import struct
import ezynq_ddr
import ezynq_registers
import ezynq_mio
# http://docs.python.org/2/howto/argparse.html
import argparse
parser = argparse.ArgumentParser()
......@@ -65,242 +65,6 @@ try:
except:
MIO_HTML_MASK=0
MIO_TEMPLATES = {
'QUADSPI':(
{'NAME':'CS0', 'TRISTATE':False, 'FAST':True, 'PULLUP':True, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((1,), (0,))},
{'NAME':'IO0', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((2,), (10,))},
{'NAME':'IO1', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((3,), (11,))},
{'NAME':'IO2', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((4,), (12,))},
{'NAME':'IO3', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((5,), (13,))},
{'NAME':'SCLK', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((6,), (9,))}),
'QUADSPI_FBCLK':(
{'NAME':'FBCLK','TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((8,), )},),
#TODO: specify FAST and PULLUP for other interfaces
'ETH':(
{'NAME':'TXCK', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((16,), (28,))},
{'NAME':'TXDO', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((17,), (29,))},
{'NAME':'TXD1', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((18,), (30,))},
{'NAME':'TXD2', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((19,), (31,))},
{'NAME':'TXD3', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((20,), (32,))},
{'NAME':'TXEN', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((21,), (33,))},
{'NAME':'RXCLK','TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((22,), (34,))},
{'NAME':'RXD0', 'TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((23,), (35,))},
{'NAME':'RXD1', 'TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((24,), (36,))},
{'NAME':'RXD2', 'TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((25,), (37,))},
{'NAME':'RXD3', 'TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((26,), (38,))},
{'NAME':'RXDV', 'TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':1, 'L1':0, 'L2':0, 'L3':0, 'PINS':((27,), (39,))}),
'MDIO':(
{'NAME':'C', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((52,),)},
{'NAME':'D', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((53,),)}), # bidir - should TRISTATE be true?
'USB':(
{'NAME':'DATA4', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((28,), (40,))},
{'NAME':'DIR', 'TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((29,), (41,))},
{'NAME':'STEP', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((30,), (42,))},
{'NAME':'NEXT', 'TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((31,), (43,))},
{'NAME':'DATA0', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((32,), (44,))},
{'NAME':'DATA1', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((33,), (45,))},
{'NAME':'DATA2', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((34,), (46,))},
{'NAME':'DATA3', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((35,), (47,))},
{'NAME':'CLK', 'TRISTATE':True, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((36,), (48,))},
{'NAME':'DATA5', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((37,), (49,))},
{'NAME':'DATA6', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((38,), (50,))},
{'NAME':'DATA7', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS':((39,), (51,))}),
'SPI':(
{'NAME':'SC', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':5, 'PINS':((16, 28, 40), (12, 24, 36, 48))},
{'NAME':'MISO','TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':5, 'PINS':((17, 29, 41), (11, 23, 35, 47))},
{'NAME':'SS0', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':5, 'PINS':((18, 30, 42), (13, 25, 37, 49))},
{'NAME':'SS1', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':5, 'PINS':((19, 31, 43), (14, 26, 38, 50))},
{'NAME':'SS2', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':5, 'PINS':((20, 32, 44), (15, 27, 39, 51))},
{'NAME':'MOSI','TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':5, 'PINS':((21, 33, 45), (10, 22, 34, 46))}),
'SDIO':(
{'NAME':'CLK', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((16, 28, 40), (12, 24, 36, 48))},
{'NAME':'CMD', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((17, 29, 41), (11, 23, 35, 47))},
{'NAME':'IO0', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((18, 30, 42), (10, 22, 34, 46))},
{'NAME':'IO1', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((19, 31, 43), (13, 25, 37, 59))},
{'NAME':'IO2', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((20, 32, 44), (14, 26, 38, 50))},
{'NAME':'IO3', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((21, 33, 45), (15, 27, 39, 51))}),
'SDIO_CD':(
{'NAME':'CD', 'TRISTATE':True, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':0, 'PINS':(
(0,1,2,3,4,5,6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,
31,32,33,34,35,36,37.38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53),
(0,1,2,3,4,5,6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,
31,32,33,34,35,36,37.38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53))},),
'SDIO_WP':(
{'NAME':'WP', 'TRISTATE':True, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':0, 'PINS':(
(0,1,2,3,4,5,6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,
31,32,33,34,35,36,37.38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53),
(0,1,2,3,4,5,6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,
31,32,33,34,35,36,37.38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53))},),
'SDIO_PWR':(
{'NAME':'PWR', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':3, 'L3':0, 'PINS':(
(0,2,4,6,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52),
(1,3,5,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37.39,41,43,45,47,49,51,53))},),
'NOR':(
{'NAME':'CS0', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((0,),)},
{'NAME':'DATA0', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((3,),)},
{'NAME':'DATA1', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((4,),)},
{'NAME':'DATA2', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((5,),)},
{'NAME':'DATA3', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((6),)},
{'NAME':'OE', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((7,),)},
{'NAME':'WE', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':2, 'PINS':((8,),)},
{'NAME':'DATA6', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((9,),)},
{'NAME':'DATA7', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((10,),)},
{'NAME':'DATA4', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((11,),)},
{'NAME':'DATA5', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((13,),)},
{'NAME':'A0', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((15,),)},
{'NAME':'A1', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((16,),)},
{'NAME':'A2', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((17,),)},
{'NAME':'A3', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((18,),)},
{'NAME':'A4', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((19,),)},
{'NAME':'A5', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((20,),)},
{'NAME':'A6', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((21,),)},
{'NAME':'A7', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((22,),)},
{'NAME':'A8', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((23,),)},
{'NAME':'A9', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((24,),)},
{'NAME':'A10', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((25,),)},
{'NAME':'A11', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((26,),)},
{'NAME':'A12', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((27,),)},
{'NAME':'A13', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((28,),)},
{'NAME':'A14', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((29,),)},
{'NAME':'A15', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((30,),)},
{'NAME':'A16', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((31,),)},
{'NAME':'A17', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((32,),)},
{'NAME':'A18', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((33,),)},
{'NAME':'A19', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((34,),)},
{'NAME':'A20', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((35,),)},
{'NAME':'A21', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((36,),)},
{'NAME':'A22', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((37,),)},
{'NAME':'A23', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((38,),)},
{'NAME':'A24', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((39,),)}),
'NOR_A25':(
{'NAME':'A25', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':1, 'L3':0, 'PINS':((1,),)},),
'NOR_CS1':(
{'NAME':'CS1', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((1,),)},),
'NAND':(
{'NAME':'CS', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((0,),)},
{'NAME':'ALE', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((2,),)},
{'NAME':'WE', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((3,),)},
{'NAME':'IO2', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((4,),)},
{'NAME':'IO0', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((5,),)},
{'NAME':'IO1', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((6,),)},
{'NAME':'CLE', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((7,),)},
{'NAME':'RD', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((8,),)},
{'NAME':'IO4', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((9,),)},
{'NAME':'IO5', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((10,),)},
{'NAME':'IO6', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((11,),)},
{'NAME':'IO7', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((12,),)},
{'NAME':'IO3', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((13,),)},
{'NAME':'BUSY','TRISTATE':True, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((14,),)}),
#NAND16 is used in addition to NAND
'NAND16':(
{'NAME':'IO8', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((16,),)},
{'NAME':'IO9', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((17,),)},
{'NAME':'IO10', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((18,),)},
{'NAME':'IO11', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((19,),)},
{'NAME':'IO12', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((20,),)},
{'NAME':'IO13', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((21,),)},
{'NAME':'IO14', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((22,),)},
{'NAME':'IO15', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':2, 'L3':0, 'PINS':((23,),)}),
'CAN':(
{'NAME':'RX', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':1, 'PINS':
((10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50), (9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53))},
{'NAME':'TX', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':1, 'PINS':
((11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51), (8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52))}),
'UART':(
{'NAME':'RX', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':7, 'PINS':
((10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50), (9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53))},
{'NAME':'TX', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':7, 'PINS':
((11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51), (8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52))}),
'I2C':(
{'NAME':'SCL', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':2, 'PINS':
((10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50), (12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52))},
{'NAME':'SDA', 'TRISTATE':False, 'FAST':False, 'PULLUP':True, 'L0':0, 'L1':0, 'L2':0, 'L3':2, 'PINS':
((11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51), (13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53))}),
'TTC':(
{'NAME':'WOUT','TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':6, 'PINS': ((18, 30, 42), (16, 28, 40))},
{'NAME':'CLK', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':6, 'PINS': ((19, 31, 43), (17, 29, 41))}),
'SWDT':(
{'NAME':'CLK', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':3, 'PINS': ((14, 26, 38, 50, 52),)},
{'NAME':'RSTO','TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':3, 'PINS': ((15, 27, 39, 51, 53),)}),
'PJTAG':(
{'NAME':'TDI', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':3, 'PINS': ((10, 22, 34, 46),)},
{'NAME':'TDO', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':3, 'PINS': ((11, 23, 35, 47),)},
{'NAME':'TCK', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':3, 'PINS': ((12, 24, 36, 48),)},
{'NAME':'TMS', 'TRISTATE':True, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':3, 'PINS': ((13, 25, 37, 49),)}),
'TPUI':( # variable number of options
{'NAME':'CLK0', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((12,24),)},
{'NAME':'CTL', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((13,25),)},
{'NAME':'DATA0', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((14,26),)},
{'NAME':'DATA1', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((15,27),)},
{'NAME':'DATA2', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((10,22),)},
{'NAME':'DATA3', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((11,23),)},
{'NAME':'DATA4', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((16,),)},
{'NAME':'DATA5', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((17,),)},
{'NAME':'DATA6', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((18,),)},
{'NAME':'DATA7', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((19,),)},
{'NAME':'DATA8', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((2,),)},
{'NAME':'DATA9', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((3,),)},
{'NAME':'DATA10', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((4,),)},
{'NAME':'DATA11', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((5,),)},
{'NAME':'DATA12', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((6,),)},
{'NAME':'DATA13', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((7,),)},
{'NAME':'DATA14', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((8,),)},
{'NAME':'DATA15', 'TRISTATE':False, 'FAST':False, 'PULLUP':False, 'L0':0, 'L1':1, 'L2':0, 'L3':0, 'PINS': ((9,),)})
}
MIO_INTERFACES=[
{'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_0', 'IFACE':'QUADSPI', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_1', 'IFACE':'QUADSPI_FBCLK','CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_QUADSPI_FBCLK', 'IFACE':'ETH', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_0', 'IFACE':'ETH', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_1', 'IFACE':'ETH', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_ETH_MDIO', 'IFACE':'MDIO', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_USB_0', 'IFACE':'USB', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_USB_1', 'IFACE':'USB', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SPI_0', 'IFACE':'SPI', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SPI_1', 'IFACE':'SPI', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SDIO_0', 'IFACE':'SDIO', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SDIO_1', 'IFACE':'SDIO', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SDCD_0', 'IFACE':'SDIO_CD', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SDCD_1', 'IFACE':'SDIO_CD', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SDWP_0', 'IFACE':'SDIO_WP', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SDWP_1', 'IFACE':'SDIO_WP', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SDPWR_0', 'IFACE':'SDIO_PWR', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SDPWR_1', 'IFACE':'SDIO_PWR', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_NOR', 'IFACE':'NOR', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_NOR_A25', 'IFACE':'NOR_A25', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_NOR_CS1', 'IFACE':'NOR_CS1', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_NAND', 'IFACE':'NAND', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_NAND16', 'IFACE':'NAND16', 'CHANNEL':0}, #requires NAND
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_CAN_0', 'IFACE':'CAN', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_CAN_1', 'IFACE':'CAN', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_CAN_ECLK_0','IFACE':'CAN_ECLK', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_CAN_ECLK_1','IFACE':'CAN_ECLK', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_UART_0', 'IFACE':'UART', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_UART_1', 'IFACE':'UART', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_I2C_0', 'IFACE':'I2C', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_I2C_1', 'IFACE':'I2C', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_TTC_0', 'IFACE':'TTC', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_TTC_1', 'IFACE':'TTC', 'CHANNEL':1},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_SWDT', 'IFACE':'SWDT', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_PJTAG', 'IFACE':'PJTAG', 'CHANNEL':0},
{'CONFIG_NAME':'CONFIG_EZYNQ_MIO_TPUI', 'IFACE':'TPUI', 'CHANNEL':0}]
MIO_ATTR=[
{'PREFIX':'CONFIG_EZYNQ_MIO_IOSTD_LVCMOS18_','PROPERTY':'IOTYPE','VALUE':'LVCMOS18'},
{'PREFIX':'CONFIG_EZYNQ_MIO_IOSTD_LVCMOS25_','PROPERTY':'IOTYPE','VALUE':'LVCMOS25'},
{'PREFIX':'CONFIG_EZYNQ_MIO_IOSTD_LVCMOS33_','PROPERTY':'IOTYPE','VALUE':'LVCMOS33'},
{'PREFIX':'CONFIG_EZYNQ_MIO_IOSTD_HSTL_', 'PROPERTY':'IOTYPE','VALUE':'HSTL'},
{'PREFIX':'CONFIG_EZYNQ_MIO_IOSTD_HSTLDIS_', 'PROPERTY':'IOTYPE','VALUE':'HSTLDIS'},
{'PREFIX':'CONFIG_EZYNQ_MIO_PULLUP_EN_', 'PROPERTY':'PULLUP','VALUE':True},
{'PREFIX':'CONFIG_EZYNQ_MIO_PULLUP_DIS_', 'PROPERTY':'PULLUP','VALUE':False},
{'PREFIX':'CONFIG_EZYNQ_MIO_FAST_', 'PROPERTY':'FAST', 'VALUE':True},
{'PREFIX':'CONFIG_EZYNQ_MIO_SLOW_', 'PROPERTY':'FAST', 'VALUE':False},
{'PREFIX':'CONFIG_EZYNQ_MIO_INOUT_', 'SPECIAL':'DIR'},
{'PREFIX':'CONFIG_EZYNQ_MIO_GPIO_OUT_', 'SPECIAL':'GPIO_OUT'}]
GPIO_MASKDATA=[
{'NAME':'MASK_DATA_0_LSW','ADDRESS':0xE000A000,'DATA':0},
{'NAME':'MASK_DATA_0_MSW','ADDRESS':0xE000A004,'DATA':0},
......@@ -335,7 +99,7 @@ ACCESSIBLE_REGISTERS=((0xe0001000,0xe0001fff), # UART1 controller registers
if args.verbosity >= 2:
print MIO_TEMPLATES
print ezynq_mio.MIO_TEMPLATES
def read_config(filename):
raw_configs = []
f = open(filename)
......@@ -356,337 +120,7 @@ def read_config(filename):
raw_configs.append({'KEY':option,'VALUE':value})
f.close()
return raw_configs
def parse_config_mio(raw_configs):
attrib_suffix='ATTRIB'
options = {}
for line in raw_configs:
option = line['KEY']
value = line['VALUE']
if QUALIFIER_CHAR in option:
option,qualifier=option.split(QUALIFIER_CHAR,1)
if not option in options:
options[option]={}
if not isinstance(options[option],dict): # make a former value a value in a dictionary
options[option]={'INTERFACE_GROUP':options[option]}
if qualifier==attrib_suffix:
value=str(value).upper()
try:
options[option]['ATTRIBS'].add(value)
except:
options[option]['ATTRIBS']=set([value])
if not 'INTERFACE_GROUP' in options[option]:
options[option]['INTERFACE_GROUP']='Y' # 'any' if not overwritten, so just setting attribute initializes interface
else:
options[option][qualifier]=value
else:
# store in the dictionary:
if option in options:
try:
options[option]['INTERFACE_GROUP'] = value #qualified pins already defined
except:
options[option] = value # not a dictionary - just overwrite
else:
options[option] = value
return options
def mio_set_defaults(mio_dflts, mio, options):
VALID_VOLTAGES = (1.8, 2.5, 3.3)
IOSTD = ('LVCMOS18', 'LVCMOS25', 'LVCMOS33')
try:
mio_dflts['MIO_0_VOLT'] = float(options['CONFIG_EZYNQ_MIO_0_VOLT'])
except (KeyError):
print "required CONFIG_EZYNQ_MIO_0_VOLT is not defined. It should be 1.8, 2.5 or 3.3"
exit (ERROR_DEFS['MISSING_CONFIG'])
if not mio_dflts['MIO_0_VOLT'] in VALID_VOLTAGES:
print 'Invalid voltage specified for MIO bank 0: CONFIG_EZYNQ_MIO_0_VOLT = ' + options['CONFIG_EZYNQ_MIO_0_VOLT']
print 'Valid values are : ' + str(VALID_VOLTAGES)
exit (ERROR_DEFS['INVALID'])
try:
mio_dflts['MIO_1_VOLT'] = float(options['CONFIG_EZYNQ_MIO_1_VOLT'])
except (KeyError):
print "required CONFIG_EZYNQ_MIO_1_VOLT is not defined. It should be 1.8, 2.5 or 3.3"
exit (ERROR_DEFS['MISSING_CONFIG'])
if not mio_dflts['MIO_1_VOLT'] in VALID_VOLTAGES:
print 'Invalid voltage specified for MIO bank 1: CONFIG_EZYNQ_MIO_1_VOLT = ' + options['CONFIG_EZYNQ_MIO_1_VOLT']
print 'Valid values are : ' + str(VALID_VOLTAGES)
exit (ERROR_DEFS['INVALID'])
iostd0 = IOSTD[VALID_VOLTAGES.index(mio_dflts['MIO_0_VOLT'])]
pullup0 = False
if 'CONFIG_EZYNQ_MIO_0_PULLUP' in options:
pullup0 = True
for i in range (0, 16):
mio[i]['IOTYPE'] = iostd0;
mio[i]['PULLUP'] = pullup0;
iostd1 = IOSTD[VALID_VOLTAGES.index(mio_dflts['MIO_1_VOLT'])]
pullup1 = False
if 'CONFIG_EZYNQ_MIO_1_PULLUP' in options:
pullup1 = True
for i in range (16, 54):
mio[i]['IOTYPE'] = iostd1;
mio[i]['PULLUP'] = pullup1;
def set_mio_interfaces(mio_interfaces, options):
for conf_iface in MIO_INTERFACES:
if conf_iface['CONFIG_NAME'] in options:
iface_name= conf_iface['IFACE']
iface_template= MIO_TEMPLATES[iface_name]
channel= conf_iface['CHANNEL']
option= options[conf_iface['CONFIG_NAME']]
# print '---->',option
if len(iface_template[0]['PINS'])>1:
print_channel=' channel '+str(channel)
else:
print_channel=''
try:
option.has_key('INTERFACE_GROUP')
except:
option={'INTERFACE_GROUP':option} # it was not a dictionary - string or number
# is the interface group as a whole used (not only individual pins)?
iface={}
if 'INTERFACE_GROUP' in option:
if option['INTERFACE_GROUP'] in "yY": # take first variant
anypin=iface_template[0]['PINS'][channel][0]
else:
anypin=int(option['INTERFACE_GROUP'])
#find if this pin belongs to specified interface/channel
# variant=-1
for func_pin in iface_template:
pins=func_pin['PINS'][channel]
if anypin in pins:
variant=pins.index(anypin)
break
else:
print 'Invalid MIO pin number '+str(anypin)+' for interface '+iface_name+print_channel+', set in '
print conf_iface['CONFIG_NAME']+" = "+str(anypin)
allowed_pins=[]
for func_pin in iface_template:
for pin in func_pin['PINS'][channel]:
allowed_pins.append(pin)
print 'Allowed MIO pins are:',allowed_pins
exit (ERROR_DEFS['NOSUCHPIN'])
for tmpl_pin in iface_template:
iface_pin={}
for key in tmpl_pin.keys():
if (key != 'NAME') and (key != 'PINS'):
iface_pin[key]=tmpl_pin[key]
iface_pin['PIN']= tmpl_pin['PINS'][channel][variant]
iface[tmpl_pin['NAME']]= iface_pin
#now process individual pins (if any) specified for the interface
for individual_pin_name in option.keys():
if not individual_pin_name in ('INTERFACE_GROUP','ATTRIBS'):
value = option[individual_pin_name]
# print individual_pin_name,value
if value[0] in 'nfNF':
value = -1
elif value[0] in 'yY':
value='y'
else:
value=int(value)
#TODO: Value may be just 'y' if there is a single option
#Traceback (most recent call last):
# File "./ezynq/ezynqcfg.py", line 455, in <module>
# set_mio_interfaces(mio_interfaces, options)
# File "./ezynq/ezynqcfg.py", line 369, in set_mio_interfaces
# anypin=int(option['INTERFACE_GROUP'])
#ValueError: invalid literal for int() with base 10: 'y'
#find if such pin name is defined for the interface
# for pin_index, tmpl_pin in enumerate(iface_template):
for tmpl_pin in iface_template:
if tmpl_pin['NAME'] == individual_pin_name:
break;
else:
print 'Signal name '+individual_pin_name+' is not defined for interface '+iface_name+' in'
print conf_iface['CONFIG_NAME']+QUALIFIER_CHAR+individual_pin_name+" = "+option[individual_pin_name]
exit (ERROR_DEFS['NOSUCHSIGNAL'])
if (value<0):
try:
del iface[individual_pin_name]
except:
pass # OK to delete non-existent?
else:
#see if pin number is valid
if value == 'y':
value=tmpl_pin['PINS'][channel][0] # first variant
if not value in tmpl_pin['PINS'][channel]:
print 'Invalid MIO pin number '+str(value)+' for interface '+iface_name+print_channel+', set in '
print conf_iface['CONFIG_NAME']+QUALIFIER_CHAR+individual_pin_name+" = "+option[individual_pin_name]
print 'Allowed MIO pins are:',tmpl_pin['PINS'][channel]
exit (ERROR_DEFS['NOSUCHPIN'])
#set new pin data
iface_pin={}
for key in tmpl_pin.keys():
if (key != 'NAME') and (key != 'PINS'):
iface_pin[key]=tmpl_pin[key]
# print 'channel=',channel,'variant=',variant,'tmpl_pin["PINS"]=',tmpl_pin['PINS']
iface_pin['PIN']= value # tmpl_pin['PINS'][channel][variant]
iface[tmpl_pin['NAME']]= iface_pin
# Now we can try to apply iface to MIO, and add it to the list
#or remove mio from function arguments and process mio_interfaces later?
if args.verbosity >= 3:
print 'name=',iface_name,' iface:'
for i, item in enumerate(iface):
print i, item, ':',iface[item]
print
if not 'ATTRIBS' in option:
option['ATTRIBS']=set()
mio_interfaces.append({'NAME':iface_name,'CHANNEL':channel, 'IFACE':iface, 'PRINT_CHANNEL':print_channel,'ATTRIBS':option['ATTRIBS']})
def config_name (iface, channel, signal):
for mi in MIO_INTERFACES:
if (mi['IFACE']==iface) and (mi['CHANNEL']==channel) :
if signal:
return mi['CONFIG_NAME']+QUALIFIER_CHAR+signal
else:
return mi['CONFIG_NAME']
def apply_mio_interfaces(mio, mio_interfaces,warn):
for iface_item in mio_interfaces:
name= iface_item['NAME']
channel=iface_item['CHANNEL']
iface=iface_item['IFACE']
print_channel=iface_item['PRINT_CHANNEL']
attribs=iface_item['ATTRIBS'] # set
for signal in iface:
pin=iface[signal]
#see if the same pin was already used in one or several interfaces
if mio[pin['PIN']]['USED_IN'] : #need to add len() >0?
for used_in in mio[pin['PIN']]['USED_IN']:
print ('MIO pin '+str(pin['PIN'])+" is previously used by interface "+used_in['NAME']+
used_in['PRINT_CHANNEL']+', signal '+used_in['SIGNAL']+'.')
print 'You may resolve the conflict by freeing one of the signals, adding one of the following lines:'
print config_name (used_in['NAME'], used_in['CHANNEL'], used_in['SIGNAL'])+'=free'
print 'or'
print config_name (name, channel, signal)+'=free'
print 'to the board configuration file\n'
if not warn:
exit (ERROR_DEFS['MIOCONFLICT'])
#add current pin usage information
mio[pin['PIN']]['USED_IN'].append({'NAME':name, 'CHANNEL':channel,'SIGNAL':signal,'PRINT_CHANNEL':print_channel})
#modify mio pin attributes
#copy attributes from the interface template (if they are defined)
for attr in pin:
if (attr != 'PIN'):
mio[pin['PIN']][attr]=pin[attr]
# {'NAME':'IO3', 'TRISTATE':False, 'FAST':True, 'PULLUP':False, 'L0':0, 'L1':0, 'L2':0, 'L3':4, 'PINS':((21, 33, 45), (15, 27, 39, 51))}),
#overwrite attributes if specified for interface in config
if 'SLOW' in attribs:
mio[pin['PIN']]['FAST']=False
if 'FAST' in attribs:
mio[pin['PIN']]['FAST']=True
if 'PULLUP' in attribs:
mio[pin['PIN']]['PULLUP']=True
if 'NOPULLUP' in attribs:
mio[pin['PIN']]['PULLUP']=False
def parse_mio(mio):
for n, pin in enumerate(mio):
value=0;
if ('TRISTATE' in pin) and pin['TRISTATE']:
value |= 1 # bit 0
if 'L0' in pin:
value |= (pin['L0'] & 1) << 1 # bit 1
if 'L1' in pin:
value |= (pin['L1'] & 1) << 2 # bit 2
if 'L2' in pin:
value |= (pin['L2'] & 3) << 3 # bits 3:4
if 'L3' in pin:
value |= (pin['L3'] & 7) << 5 # bits 5:7
if ('FAST' in pin) and pin['FAST']:
value |= (1<<8) # bit 8
if ('IOTYPE' in pin):
if pin['IOTYPE']=='LVCMOS18':
value |= (1<<9) # bits 9:11
elif pin['IOTYPE']=='LVCMOS25':
value |= (2<<9) # bits 9:11
elif pin['IOTYPE']=='LVCMOS33':
value |= (3<<9) # bits 9:11
elif pin['IOTYPE']=='HSTL':
value |= (4<<9) # bits 9:11
elif pin['IOTYPE']=='HSTLDIS':
value |= (4<<9) | (1<<13) # bits 9:11, bit 13
else:
print 'Invalid I/O standard: '+pin['IOTYPE']+' for MIO pin#'+n
exit (-1)
if ('PULLUP' in pin) and pin['PULLUP']:
value |= (1<<12) # bit 12
pin['VALUE']=value # or mio[n]['VALUE']=value ???
pin['HEX']=hex(value) # or mio[n]['VALUE']=value ???
#CONFIG_EZYNQ_MIO_IOSTD_LVCMOS18_NN= y # will overwrite defaults, last numeric specifies MIO pin number
#CONFIG_EZYNQ_MIO_IOSTD_LVCMOS25_NN= y # will overwrite defaults
#CONFIG_EZYNQ_MIO_IOSTD_LVCMOS33_NN= y # will overwrite defaults
#CONFIG_EZYNQ_MIO_IOSTD_HSTL_NN= y # will overwrite defaults
#CONFIG_EZYNQ_MIO_IOSTD_HSTLDIS_NN= y # will overwrite defaults
#CONFIG_EZYNQ_MIO_PULLUP_EN_NN= y # will overwrite defaults
#CONFIG_EZYNQ_MIO_PULLUP_DIS_NN= y # will overwrite defaults
#CONFIG_EZYNQ_MIO_FAST_NN= y # will overwrite defaults
#CONFIG_EZYNQ_MIO_INOUT_NN= 'IN' # 'OUT', 'BIDIR'
#CONFIG_EZYNQ_MIO_GPIO_OUT_NN= 0 # Set selected GPIO output to 0/1
def set_mio_attribs(mio,options):
attribs={}
for option in options:
for attrib_entry in MIO_ATTR:
prefix=attrib_entry['PREFIX']
# print prefix,' <->', option, option[:len(prefix)]
if option[:len(prefix)]==prefix:
if not prefix in attribs:
attribs[prefix]={}
# print prefix,options[option],option[len(prefix):]
try:
key=int(option[len(prefix):])
except:
print 'Invalid pin number ',option[len(prefix):],' in',option
exit (ERROR_DEFS['NOSUCHPIN)'])
attribs[prefix][key]=options[option]
break
# print '------- attribs -----'
# for a in attribs:
# print a,attribs[a]
#set defined attrinutes for MIO pins
for attr in MIO_ATTR:
if ('PROPERTY' in attr) and (attr['PREFIX'] in attribs):
for pin in attribs[attr['PREFIX']]:
if (pin in range(len(mio))):
mio[pin][attr['PROPERTY']]=attr['VALUE']
# print '***',attr['PROPERTY'],pin,attr['VALUE']
else:
print attr['PREFIX']+str(pin)+': pin number',pin,' out of range 0...53'
exit (ERROR_DEFS['NOSUCHPIN'])
#set IN, OUT, BIDIR (INOUT) parameters
elif ('SPECIAL' in attr) and (attr['SPECIAL']=='DIR') and (attr['PREFIX'] in attribs):
for pin in attribs[attr['PREFIX']]:
value=attribs[attr['PREFIX']][pin]
value=value.upper()
if (value=='INOUT') or (value=='BIDIR'):
value = 'BIDIR'
elif (value=='IN') or (value=='INPUT'):
value = 'IN'
elif (value=='OUT') or (value=='OUTPUT'):
value = 'OUT'
else:
print 'Invalid MIO pin polarity in',attr['PREFIX']+str(pin),'=',value
print 'Polarity can only be IN, OUT or BIDIR'
exit (ERROR_DEFS['INOUT'])
if (pin==7) or (pin==8) and (value!='OUT'):
print 'Invalid MIO pin polarity in',attr['PREFIX']+str(pin),'=',value
print 'Polarity for MIO pins 7 and 8 can only be OUT'
exit (ERROR_DEFS['INOUT'])
mio[pin]['INOUT']=value #Where is it used?
if value=='IN':
mio[pin]['TRISTATE']=True
elif ('SPECIAL' in attr) and (attr['SPECIAL']=='GPIO_OUT') and (attr['PREFIX'] in attribs):
for pin in attribs[attr['PREFIX']]:
value=attribs[attr['PREFIX']][pin]
# print pin, value
if (value!=0) and (value!='0'):
value=1
else:
value=0
# print 'value=',value
mio[pin]['DATA_OUT']=value #Where is it used?
def verify_register_accessible(address):
for interval in ACCESSIBLE_REGISTERS:
if (address >= interval[0]) and (address <= interval[1]):
......@@ -694,127 +128,21 @@ def verify_register_accessible(address):
return True
else:
return False
#ACCESSIBLE_REGISTERS
def output_mio(registers,f,mio,MIO_HTML_MASK):
if not registers is False:
for mio_pin in mio:
registers.append({'ADDRESS':mio_pin['ADDR'],'DATA':mio_pin['VALUE']})
if not f:
return
f.write ('<H2>MIO pins map</H2>\n')
f.write('<table border="1">\n')
f.write(' <tr>\n')
f.write(' <th>MIO<br/>pin</th>')
if MIO_HTML_MASK & 1:
f.write('<th>address</th>')
if MIO_HTML_MASK & 2:
f.write('<th>PULLUP</th>')
f.write('<th>FAST</th>')
f.write('<th>TRISTATE</th>')
f.write('<th>IOSTD</th>')
if MIO_HTML_MASK & 4:
f.write('<th>interface</th>')
f.write(' <th>value</th>')
if MIO_HTML_MASK & 8:
f.write('<th>data<br/>out</th>')
for c in mio_interfaces:
f.write('<th>'+c['NAME']+'<br/>'+c['PRINT_CHANNEL']+'&nbsp;</th>')
f.write(' </tr>\n')
for pinnum,mio_pin in enumerate(mio):
f.write('<th>'+str(pinnum)+'</th>')
if MIO_HTML_MASK & 1:
f.write('<td>'+hex(mio_pin['ADDR'])+'</td>')
if MIO_HTML_MASK & 2:
f.write('<td align="center">'+'-Y'[(mio_pin['VALUE'] >>12) & 1]+'</td>')
f.write('<td align="center">'+'-Y'[(mio_pin['VALUE'] >> 8) & 1]+'</td>')
f.write('<td align="center">'+'-Y'[(mio_pin['VALUE'] >> 0) & 1]+'</td>')
iostd=('INVALID','LVCMOS18','LVCMOS25','LVCMOS33','HSTL','INVALID','INVALID',
'INVALID')[(mio_pin['VALUE']>>9)&7]
disRsv=('','_DISRSV')[(mio_pin['VALUE']>>13)&1]
f.write('<td>'+iostd+disRsv+'</td>')
if MIO_HTML_MASK & 4:
if not mio_pin['USED_IN']:
f.write('<td align="center">-</td>')
else:
used_in=mio_pin['USED_IN'][len(mio_pin['USED_IN'])-1]
multichannel=len(used_in['PRINT_CHANNEL'])>0
f.write('<td align="center">'+(used_in['NAME']+('',' '+str(used_in['CHANNEL']))[multichannel])+'</td>')
# f.write('<td>'+str(((mio_pin['VALUE'] & (1<< 8)))!=0)+'</td>')
# f.write('<td>'+str(((mio_pin['VALUE'] & (1<< 0)))!=0)+'</td>')
f.write('<td>'+hex(mio_pin['VALUE'])+'</td>')
if MIO_HTML_MASK & 8:
if 'DATA_OUT' in mio_pin:
data_out= str(mio_pin['DATA_OUT'])
else:
data_out='-'
f.write('<td>'+ data_out+'</td>')
for iface in mio_interfaces:
signals=iface['IFACE']
for signal in signals:
if signals[signal]['PIN']==pinnum:
f.write('<td>'+signal+'</td>')
break
else:
f.write('<td>&nbsp;</td>')
f.write(' </tr>\n')
f.write('</table>\n')
def output_gpio_out(registers,f,MIO_HTML_MASK):
if f:
f.write ('<H2>GPIO Output mask/data registers</H2>\n')
f.write('<table border="1">\n')
f.write(' <tr><th>Register name</th><th>Address</th><th>Data</th></tr>\n')
for i,word in enumerate (GPIO_MASKDATA):
en=0
d=0
for shft in range (16):
pinnum=16*i+shft
if not pinnum in range (len(mio)):
break
if 'DATA_OUT' in mio[pinnum]:
en |= (1<<shft)
if mio[16*i+shft]['DATA_OUT']:
d |= (1<<shft)
mask= en ^ 0xffff
data= (mask<<16) | d
registers.append({'ADDRESS':word['ADDRESS'],'DATA':data})
if f:
f.write(' <tr><td>'+word['NAME']+'</td><td>'+hex(word['ADDRESS'])+'</td><td>'+hex(data)+'</td></tr>\n')
if f:
f.write(' </table>\n')
#Can not be used in register initialization of the RBL
def output_slcr_lock(registers,f,lock,MIO_HTML_MASK):
if f:
f.write ('<H2>SLCR lock/unlock</H2>\n')
f.write('<table border="1">\n')
f.write(' <tr><th>Register name</th><th>Address</th><th>Data</th></tr>\n')
# for i,word in enumerate (GPIO_MASKDATA):
word=SLCR_LOCK[lock!=0]
# print word
registers.append({'ADDRESS':word['ADDRESS'],'DATA':word['DATA']})
if f:
f.write(' <tr><td>'+word['NAME']+'</td><td>'+hex(word['ADDRESS'])+'</td><td>'+hex(word['DATA'])+'</td></tr>\n')
if f:
f.write(' </table>\n')
#### Need to be modified for new format of register setup
# def uart_remote_loopback(registers,f,uart_num,MIO_HTML_MASK):
# if f:
# f.write ('<H2>UART'+str(uart_num)+' remote loopback</H2>\n')
# f.write('<table border="1">\n')
# f.write(' <tr><th>Register name</th><th>Address</th><th>Data</th></tr>\n')
# word={'NAME':'UART'+str(uart_num)+"_mode_reg0",'ADDRESS':(0xe0000004,0xe0001004)[uart_num!=0],'DATA':0x320}
# # print word
# registers.append({'ADDRESS':word['ADDRESS'],'DATA':word['DATA']})
# if f:
# f.write(' <tr><td>'+word['NAME']+'</td><td>'+hex(word['ADDRESS'])+'</td><td>'+hex(word['DATA'])+'</td></tr>\n')
# if f:
# f.write(' </table>\n')
def uart_remote_loopback(registers,f,uart_num,MIO_HTML_MASK):
if f:
f.write ('<H2>UART'+str(uart_num)+' remote loopback</H2>\n')
f.write('<table border="1">\n')
f.write(' <tr><th>Register name</th><th>Address</th><th>Data</th></tr>\n')
word={'NAME':'UART'+str(uart_num)+"_mode_reg0",'ADDRESS':(0xe0000004,0xe0001004)[uart_num!=0],'DATA':0x320}
# print word
registers.append({'ADDRESS':word['ADDRESS'],'DATA':word['DATA']})
if f:
f.write(' <tr><td>'+word['NAME']+'</td><td>'+hex(word['ADDRESS'])+'</td><td>'+hex(word['DATA'])+'</td></tr>\n')
if f:
f.write(' </table>\n')
class Image(dict):
def __init__(self, *args, **kwargs):
......@@ -832,7 +160,13 @@ class Limage(list):
self.waddr += 1
def image_generator (image, registers, user_def,ocm_offset,ocm_len,start_exec):
def image_generator (image,
reg_sets, # registers,
options,
user_def,
ocm_offset,
ocm_len,
start_exec):
reserved0044=0;
if 'CONFIG_EZYNQ_RESERVED44' in options: reserved0044= int(options['CONFIG_EZYNQ_RESERVED44'],0)
......@@ -903,17 +237,21 @@ def image_generator (image, registers, user_def,ocm_offset,ocm_len,start_exec):
#initialize registers
if args.verbosity >= 1: print 'Number of registers to initialize',len(registers)
if len (registers)>256:
print 'Too many registers to initiAlize, only 256 allowed,',len(registers),'> 256'
if args.verbosity >= 1: print 'Number of registers to initialize',len(reg_sets)
if len (reg_sets)>256:
print 'Too many registers to initialize, only 256 allowed,',len(reg_sets),'> 256'
waddr=0xa0/4
for register in registers:
if not verify_register_accessible (register['ADDRESS']):
print 'Tried to set non-accessible register', hex(register['ADDRESS']),' with data ', hex(register['DATA'])
# new_sets.append((addr,data,mask,self.module_name,register_name,self.defs[register_name]))
for register in reg_sets:
addr=register[0]
data=register[1]
if not verify_register_accessible (addr):
print 'Tried to set non-accessible register', hex(addr),' with data ', hex(data)
exit (ERROR_DEFS['NONACCESSIBLE_REGISTER'])
image[waddr]=register['ADDRESS']
image[waddr]=addr
waddr+=1
image[waddr]=register['DATA']
image[waddr]=data
waddr+=1
#Fill in FFs for unused registers
while waddr < (0x8c0/4):
......@@ -940,101 +278,67 @@ def write_image(image,name):
#=========================
raw_configs=read_config(args.configs)
raw_options={n['KEY']:n['VALUE'] for n in raw_configs}
permit_undefined_bits=False
force=True #False
warn_notfit=True # False
regs_masked=[]
ddr=ezynq_ddr.EzynqDDR(regs_masked,permit_undefined_bits, force, warn_notfit)
ddr.parse_parameters(raw_configs)
##ddr.parse_ddriob_raw_register_set(raw_configs,QUALIFIER_CHAR,force,warn_notfit)
##ddr.parse_ddrc_raw_register_set(raw_configs,QUALIFIER_CHAR,force,warn_notfit)
#ddr.print_html_registers(html_file, show_bit_fields=True, show_comments=True)
#class EzynqDDR:
# def __init__(self,permit_undefined_bits=False,force=False,warn=False):
# def parse_raw_register_set(self,raw_configs,qualifier_char,force=True,warn=True):
# def print_html_registers(self, html_file, show_bit_fields=True, show_comments=True):
mio_regs=ezynq_mio.EzynqMIO(args.verbosity,QUALIFIER_CHAR,[],permit_undefined_bits) # does not use regs_masked
mio_regs.process_mio(raw_configs,WARN) # does not use regs_masked
ddr=ezynq_ddr.EzynqDDR([],permit_undefined_bits, force, warn_notfit) #regs_masked are just []
ddr.parse_parameters(raw_configs)
options = parse_config_mio(raw_configs)
if args.verbosity >= 3:
print options
if args.verbosity >= 1:
for i, conf in enumerate(options):
print i, conf, options[conf]
mio_dflts = {'MIO_0_VOLT':0, 'MIO_1_VOLT':0, 'MIO_0_PULLUP':False, 'MIO_1_PULLUP':False};
mio = [{'USED_IN':[], 'IOTYPE':'', 'PULLUP':False, 'FAST':False, 'TRISTATE':False, 'L0':0, 'L1':0, 'L2':0, 'L3':0, 'ADDR':(0xf8000700+k*4), 'HADDR':hex(0xf8000700+k*4)} for k in range(54)]
mio_set_defaults(mio_dflts, mio, options)
mio_interfaces=[]
set_mio_interfaces(mio_interfaces, options)
#populate_mio(mio, mio_interfaces, options,WARN)
apply_mio_interfaces(mio, mio_interfaces,WARN)
set_mio_attribs(mio,options)
parse_mio(mio)
#set MIO pin options and initial value for GPIO output
if args.verbosity >= 1:
print '\n===== mio_interfaces === '
#print mio_interfaces
for i, iface in enumerate(mio_interfaces):
print '-------------'
print 'i=',i, " iface['NAME']=",iface['NAME'],' channel=',iface['CHANNEL'],' attribs:',iface['ATTRIBS']
for pin in iface['IFACE']:
print pin,':',iface['IFACE'][pin]
print '\n===== mio === '
for i, mio_pin in enumerate(mio):
print i, mio_pin
print mio_dflts
registers=[] # list of register address/data pairs to be included in the boot fil
#TODO - match HTML and binary data sequence, set the initialization order
#store_mio (mio, registers)
#if False and MIO_HTML:
if MIO_HTML:
f=open(MIO_HTML,'w')
else:
f=False
#output_slcr_lock(registers,f,False,MIO_HTML_MASK) #prohibited by RBL
output_mio(registers,f,mio,MIO_HTML_MASK)
#output_slcr_lock(registers,f,False,MIO_HTML_MASK) #prohibited by RBL
mio_regs.output_mio(f,MIO_HTML_MASK)
# def process_mio(self,raw_configs,warn):
# def output_mio(self,f,MIO_HTML_MASK)
# setregs_mio(self,current_reg_sets,force=True):
#output_mio(registers,f,mio,MIO_HTML_MASK)
ddr.calculate_dependent_pars()
ddr.pre_validate() # before applying default values (some timings should be undefined, not defaults)
ddr.check_missing_features() #and apply defualt values
ddr.check_missing_features() #and apply default values
ddr.html_list_features(f) #verify /fix values after defaults are applied
#ddr.ddr_init_memory(current_reg_sets,force=False,warn=False): # will program to sequence 'MAIN'
ddr.ddr_init_memory([],False,False) # will program to sequence 'MAIN'
reg_sets=ddr.get_new_register_sets()
#ezynq_registers.print_html_reg_header(f, title, show_bit_fields=True, show_comments=True,filter_fields=True)
ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
#print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comments=True,filter_fields=True):
ezynq_registers.print_html_reg_footer(f)
reg_sets=[]
reg_sets=mio_regs.setregs_mio(reg_sets,force) # reg Sets include now MIO
num_mio_regs=len(reg_sets)
#adding ddr registers
ddr.ddr_init_memory(reg_sets,False,False)
#Collecting registers for output
reg_sets=ddr.get_new_register_sets() #all - mio and ddr
ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
#ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f)
#ddr.print_html_registers(f, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) #filter_fields=True
ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f)
#output_gpio_out(registers,f,MIO_HTML_MASK) #prohibited by RBL
#output_slcr_lock(registers,f,True,MIO_HTML_MASK) #prohibited by RBL
if 'CONFIG_EZYNQ_UART_LOOPBACK_0' in options: uart_remote_loopback(registers,f, 0,MIO_HTML_MASK)
if 'CONFIG_EZYNQ_UART_LOOPBACK_1' in options: uart_remote_loopback(registers,f, 1,MIO_HTML_MASK)
#TODO: Need to be modified for the new format
# if 'CONFIG_EZYNQ_UART_LOOPBACK_0' in raw_options: uart_remote_loopback(registers,f, 0,MIO_HTML_MASK)
# if 'CONFIG_EZYNQ_UART_LOOPBACK_1' in raw_options: uart_remote_loopback(registers,f, 1,MIO_HTML_MASK)
if f:
f.write('<h4>Total number of registers set up in the RBL header is <b>'+str(len(reg_sets))+"</b> of maximal 256</h4>")
if MIO_HTML:
f.close
if args.verbosity >= 1:
print registers
#if args.verbosity >= 1:
# print registers
image =[ 0 for k in range (0x8c0/4)]
#image_generator (image, registers, user_def,start_offset,ocm_len,start_exec)
......@@ -1044,11 +348,13 @@ image =[ 0 for k in range (0x8c0/4)]
#CONFIG_EZYNQ_START_EXEC= 0x20 # number of bytes to load to the OCM memory, <= 0x30000
image_generator (image,
registers,
int(options['CONFIG_EZYNQ_BOOT_USERDEF'],0), # user_def
int(options['CONFIG_EZYNQ_BOOT_OCM_OFFSET'],0), # ocm_offset,
int(options['CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH'],0), #ocm_len,
int(options['CONFIG_EZYNQ_START_EXEC'],0)) #start_exec)
reg_sets, #
#registers,
raw_options,
int(raw_options['CONFIG_EZYNQ_BOOT_USERDEF'],0), # user_def
int(raw_options['CONFIG_EZYNQ_BOOT_OCM_OFFSET'],0), # ocm_offset,
int(raw_options['CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH'],0), #ocm_len,
int(raw_options['CONFIG_EZYNQ_START_EXEC'],0)) #start_exec)
if args.outfile:
write_image(image,args.outfile)
# print int(hex(1234567),0) # works for decimal and hex
......
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