Commit 70840fd7 authored by Andrey Filippov's avatar Andrey Filippov

added settings for vdt (common for fpga projects, go to fpga workspaces)

parent 66b991b4
......@@ -10,6 +10,6 @@ rootfs-elphel
tools
bootable-images
projects.json
.project
.pydevproject
.settings
/scripts/.project
/scripts/.pydevproject
/scripts/.settings
ClearProblemsOnToolStart.Enable=true
Color.Default=00,00,00
Color.DisabledCode=230,230,230
Debug.Closure=false
Debug.Disabled=false
Debug.Launching=false
Debug.Other=false
Debug.Parsing=false
Debug.Preprocessor=false
Debug.ToolsSequence=false
DisabledCode.Enable=true
Parser.MinReparse=945
Parser.OnType=false
Style.indentSize=4
eclipse.preferences.version=1
......@@ -34,9 +34,16 @@ import sys
import subprocess
import datetime
import xml.etree.ElementTree
#import shutil
from distutils.dir_util import copy_tree
#import distutils
def main():
workspace = '../workspace-elphel393'
workspace_fpga = '../workspace-elphel393_fpga'
project_paths = "./setup_eclipse_paths.xml"
project_paths_fpga = "./setup_eclipse_fpga_paths.xml"
fpga_to_workspace = "fpga-elphel/eclipse_workspace_setup"
continue_setup = False # True # disable later
argv = sys.argv
print (argv)
......@@ -69,7 +76,10 @@ The program will not overwrite or modify any existing workspace.
if (len(argv) > 2):
workspace = argv[2]
fpga= "fpga" in workspace
if fpga:
print ("Processing FPGA projects")
project_paths = project_paths_fpga
workspace = os.path.abspath(workspace)
need_import = True
if os.path.exists(workspace):
......@@ -100,6 +110,18 @@ The program will not overwrite or modify any existing workspace.
if return_code > 0:
print ("Can not continuie on error")
return 1
if fpga:
# project_paths = project_paths_fpga
print ("Copying VDT settings (",fpga_to_workspace,") to workspace (",workspace,")")
# shutil.copytree(fpga_to_workspace+"/.metadata", workspace+"/.metadata")
# distutils.dir_util.copy_tree(fpga_to_workspace,workspace)
copy_tree(fpga_to_workspace,workspace)
'''
cp -r elphel393/fpga-elphel/eclipse_workspace_setup/.metadata ./workspace-elphel393-fpga-03
'''
#creating workspace/.metadata/.plugins/org.eclipse.core_runtime/.settings/org.eclipse.egit.core.prefs
egit_prefs_path = os.path.join(workspace,".metadata",".plugins","org.eclipse.core.runtime",".settings","org.eclipse.egit.core.prefs")
egit_prefs="GitRepositoriesView.GitDirectories="
......@@ -172,3 +194,6 @@ The program will not overwrite or modify any existing workspace.
if __name__ == "__main__":
sys.exit(main())
"""
eyesis@eyesis-SH87R:~/nc393/elphel393$ ./setup_eclipse.py /home/eyesis/eclipse/jee-oxygen/eclipse/ ../workspace-elphel393-fpga setup_eclipse_fpga_paths.xml
"""
\ No newline at end of file
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