organized new/debug files (7e44243b) · Commits · Elphel / eddr3

.gitignore

+3 −1

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		@@ -4,4 +4,6 @@ vivado_*
		syntax_*
		simulation/*
		ise_*

		attic/*
		IVERILOG_INCLUDE.v
		eddr3.prj
		No newline at end of file

.project

+15 −15

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		@@ -62,77 +62,77 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140607175804607.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140607175804607.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140607175804607.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140607175804607.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140607175804607.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140607175804607.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140607160650782.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140607173533434.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140607175804607.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140607173533434.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140607175804607.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140607160728042.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140607173533434.log</location>
		</link>
		<link>
		<name>vivado_state/eddr3-opt-phys.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140607160728042.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140607175804607.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-place.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140607160728042.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140607175804607.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-route.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140607160728042.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140607175804607.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-synth.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140607005118430.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140607173533434.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

.pydevproject

0 → 100644

+5 −0

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		<?xml version="1.0" encoding="UTF-8" standalone="no"?>
		<?eclipse-pydev version="1.0"?><pydev_project>
		<pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property>
		<pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property>
		</pydev_project>

ddr_refresh.v

0 → 100644

+63 −0

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		/*******************************************************************************
		* Module: ddr_refresh
		* Date:2014-06-02
		* Author: Andrey Filippov
		* Description: DDR3 memory refresh request module
		*
		* Copyright (c) 2014 Elphel, Inc.
		* ddr_refresh.v is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation, either version 3 of the License, or
		* (at your option) any later version.
		*
		* ddr_refresh.v is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program. If not, see <http://www.gnu.org/licenses/> .
		*******************************************************************************/
		`timescale 1ns/1ps

		module ddr_refresh(
		input rst,
		input clk,
		input [7:0] refresh_period, // in 16*clk
		input set, // and reset counters
		output want, // turns off next cycle after grant (or stays on if more are needed)
		output need,
		input grant // 1 cycle
		);
		reg [3:0] pre_div;
		reg [4:0] pending_rq; // can accumulate up to 31 requests, datasheet allows up to 16
		reg [7:0] period_cntr;
		reg cry;
		wire over=(period_cntr == 0) && cry;
		reg refresh_due;
		assign want = pending_rq != 0;
		assign need = pending_rq[4:3] != 0;
		always @ (posedge rst or posedge clk) begin
		if (rst) pre_div <= 0;
		else if (set) pre_div <= 0;
		else pre_div <= pre_div +1;

		if (rst) cry <= 0;
		else if (set) cry <= 0;
		else cry <= (pre_div == 4'hf);

		if (rst) period_cntr <= 0;
		else if (set) period_cntr <= 0;
		else if (over) period_cntr <= refresh_period;
		else if (cry) period_cntr <= period_cntr -1;

		if (rst) refresh_due <= 0;
		else refresh_due <= over;

		if (rst) pending_rq <= 0;
		else if (set) pending_rq <= 0;
		else if ( refresh_due && !grant) pending_rq <= pending_rq+1;
		else if (!refresh_due && grant) pending_rq <= pending_rq-1;
		end
		endmodule

ddrc_test01.v

+2 −2

Original line number	Diff line number	Diff line
		@@ -369,13 +369,13 @@ assign gpio_in={

		phy_locked_mmcm, // 1 1
		phy_locked_pll, // 1 1
		phy_dly_ready, // 1 0
		phy_dci_ready, // 1 0
		phy_dly_ready, // 1 0

		locked_mmcm, // 1 1
		locked_pll, // 1 1
		dly_ready, // 1 0
		dci_ready, // 1 0
		dly_ready, // 1 0

		ps_out[7:4], // 4'b0 input[7:0] 4'b0

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