debugging, next snapshot (3d67d687) · Commits · Elphel / eddr3

.project

+8 −8

Original line number	Original line	Diff line number	Diff line
	@@ -51,7 +51,7 @@
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140522152648076.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140522174846453.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	@@ -61,12 +61,12 @@
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140522152648076.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140522174846453.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140522152648076.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140522174846453.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	@@ -76,7 +76,7 @@
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140522152648076.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140522174846453.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	@@ -86,7 +86,7 @@
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140522152648076.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140522174846453.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportImplemented.log</name>		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
	@@ -96,7 +96,7 @@
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportSynthesis.log</name>		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140522152648076.log</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140522174846453.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/eddr3-opt-phys.dcp</name>		<name>vivado_state/eddr3-opt-phys.dcp</name>
	@@ -106,7 +106,7 @@
	<link>		<link>
	<name>vivado_state/eddr3-place.dcp</name>		<name>vivado_state/eddr3-place.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140522152648076.dcp</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140522174846453.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/eddr3-route.dcp</name>		<name>vivado_state/eddr3-route.dcp</name>
	@@ -116,7 +116,7 @@
	<link>		<link>
	<name>vivado_state/eddr3-synth.dcp</name>		<name>vivado_state/eddr3-synth.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140522152648076.dcp</location>		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140522174846453.dcp</location>
	</link>		</link>
	</linkedResources>		</linkedResources>
	</projectDescription>		</projectDescription>

ddrc_control.v

+30 −4

Original line number	Original line	Diff line number	Diff line
	@@ -61,7 +61,11 @@ module ddrc_control #(
	parameter PAGES_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns		parameter PAGES_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns
	parameter CMDA_EN_REL = 'h022, // address to enable('h823)/disable('h822) command/address outputs		parameter CMDA_EN_REL = 'h022, // address to enable('h823)/disable('h822) command/address outputs
	parameter CMDA_EN_REL_MASK = 'h3fe, // address mask for command/address outputs		parameter CMDA_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
	parameter EXTRA_REL = 'h024, // address to set extra parameters (currently just inv_clk_div)		parameter SDRST_ACT_REL = 'h024, // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory
			parameter SDRST_ACT_REL_MASK ='h3fe, // address mask for reset DDR3
			parameter CKE_EN_REL = 'h026, // address to enable('h827)/disable('h826) CKE signal to memory
			parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
			parameter EXTRA_REL = 'h028, // address to set extra parameters (currently just inv_clk_div)
	parameter EXTRA_REL_MASK = 'h3ff // address mask for extra parameters		parameter EXTRA_REL_MASK = 'h3ff // address mask for extra parameters
	)(		)(
	input clk,		input clk,
	@@ -85,7 +89,10 @@ module ddrc_control #(
	output ld_delay, // write dly_data to dly_address, one mclk active pulse		output ld_delay, // write dly_data to dly_address, one mclk active pulse
	output dly_set, // transfer (activate) all delays simultaneosly, 1 mclk pulse		output dly_set, // transfer (activate) all delays simultaneosly, 1 mclk pulse
	// control: additional signals		// control: additional signals
	output cmda_tri, // tri-state all command and address lines to DDR chip		output cmda_en, // tri-state all command and address lines to DDR chip
			output ddr_rst, // generate DDR3 memory reset signal
			output ddr_cke, // control DDR3 memory CKE signal

	output inv_clk_div, // invert clk_div to ISERDES		output inv_clk_div, // invert clk_div to ISERDES
	output [ 7:0] dqs_pattern, // DQS pattern during write (normally 8'h55)		output [ 7:0] dqs_pattern, // DQS pattern during write (normally 8'h55)
	output [ 7:0] dqm_pattern, // DQM pattern (just for testing, should be 8'h0)		output [ 7:0] dqm_pattern, // DQM pattern (just for testing, should be 8'h0)
	@@ -108,6 +115,12 @@ module ddrc_control #(
	localparam PAGES_ADDR_MASK = CONTROL_ADDR_MASK \| PAGES_REL_MASK; // address mask to set DQM and DQS patterns		localparam PAGES_ADDR_MASK = CONTROL_ADDR_MASK \| PAGES_REL_MASK; // address mask to set DQM and DQS patterns
	localparam CMDA_EN_ADDR = CONTROL_ADDR \| CMDA_EN_REL; // address to enable('h823)/disable('h822) command/address outputs		localparam CMDA_EN_ADDR = CONTROL_ADDR \| CMDA_EN_REL; // address to enable('h823)/disable('h822) command/address outputs
	localparam CMDA_EN_ADDR_MASK = CONTROL_ADDR_MASK \| CMDA_EN_REL_MASK; // address mask for command/address outputs		localparam CMDA_EN_ADDR_MASK = CONTROL_ADDR_MASK \| CMDA_EN_REL_MASK; // address mask for command/address outputs

			localparam SDRST_ACT_ADDR = CONTROL_ADDR \| SDRST_ACT_REL; // address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory
			localparam SDRST_ACT_ADDR_MASK =CONTROL_ADDR_MASK \| SDRST_ACT_REL_MASK; // address mask for reset DDR3
			localparam CKE_EN_ADDR = CONTROL_ADDR \| CKE_EN_REL; // address to enable('h827)/disable('h826) CKE signal to memory
			localparam CKE_EN_ADDR_MASK = CONTROL_ADDR_MASK \| CKE_EN_REL_MASK; // address mask for CKE

	localparam EXTRA_ADDR = CONTROL_ADDR \| EXTRA_REL; // address to set extra parameters (currently just inv_clk_div)		localparam EXTRA_ADDR = CONTROL_ADDR \| EXTRA_REL; // address to set extra parameters (currently just inv_clk_div)
	localparam EXTRA_ADDR_MASK = CONTROL_ADDR_MASK \| EXTRA_REL_MASK; // address mask for extra parameters		localparam EXTRA_ADDR_MASK = CONTROL_ADDR_MASK \| EXTRA_REL_MASK; // address mask for extra parameters

	@@ -133,6 +146,9 @@ module ddrc_control #(
	reg [ 1:0] port1_page_r; // port 1 buffer write page (to be controlled by arbiter later, set to 2'b0)		reg [ 1:0] port1_page_r; // port 1 buffer write page (to be controlled by arbiter later, set to 2'b0)
	reg [ 1:0] port1_int_page_r; // port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0)		reg [ 1:0] port1_int_page_r; // port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0)
	reg cmda_en_r; // enable (tri-state off) all command and address lines to DDR chip		reg cmda_en_r; // enable (tri-state off) all command and address lines to DDR chip
			reg ddr_rst_r; // generate DDR3 memory reset
			reg ddr_cke_r; // enable CKE to memory

	reg inv_clk_div_r; // invert clk_div to ISERDES		reg inv_clk_div_r; // invert clk_div to ISERDES

	assign ld_delay = dly_ld_r;		assign ld_delay = dly_ld_r;
	@@ -141,7 +157,7 @@ module ddrc_control #(
	assign dly_addr = waddr_fifo_out_r[ 6:0]; //WARNING: [Synth 8-3936] Found unconnected internal register 'waddr_fifo_out_r_reg' and it is trimmed from '12' to '7' bits. [ddrc_control.v:101]		assign dly_addr = waddr_fifo_out_r[ 6:0]; //WARNING: [Synth 8-3936] Found unconnected internal register 'waddr_fifo_out_r_reg' and it is trimmed from '12' to '7' bits. [ddrc_control.v:101]
	assign run_addr = wdata_fifo_out_r[10:0];		assign run_addr = wdata_fifo_out_r[10:0];
	assign run_chn = waddr_fifo_out_r[3:0];		assign run_chn = waddr_fifo_out_r[3:0];
	assign run_seq = run_seq_r;		assign run_seq = run_seq_r && !ddr_rst;

	assign busy=busy_r && (start_wburst?(((pre_waddr ^ BUSY_WR_ADDR) & BUSY_WR_ADDR_MASK)==0): selected_busy);		assign busy=busy_r && (start_wburst?(((pre_waddr ^ BUSY_WR_ADDR) & BUSY_WR_ADDR_MASK)==0): selected_busy);

	@@ -151,7 +167,9 @@ module ddrc_control #(
	assign port0_int_page = port0_int_page_r[1:0];		assign port0_int_page = port0_int_page_r[1:0];
	assign port1_page = port1_page_r[1:0];		assign port1_page = port1_page_r[1:0];
	assign port1_int_page = port1_int_page_r[1:0];		assign port1_int_page = port1_int_page_r[1:0];
	assign cmda_tri = ~cmda_en_r;		assign cmda_en = cmda_en_r;
			assign ddr_rst= ddr_rst_r;
			assign ddr_cke= ddr_cke_r;
	assign inv_clk_div = inv_clk_div_r;		assign inv_clk_div = inv_clk_div_r;

	always @ (posedge clk or posedge rst) begin		always @ (posedge clk or posedge rst) begin
	@@ -202,6 +220,14 @@ module ddrc_control #(
	else if (fifo_re && (((waddr_fifo_out ^ CMDA_EN_ADDR) & CMDA_EN_ADDR_MASK)==0))		else if (fifo_re && (((waddr_fifo_out ^ CMDA_EN_ADDR) & CMDA_EN_ADDR_MASK)==0))
	cmda_en_r <= waddr_fifo_out[0];		cmda_en_r <= waddr_fifo_out[0];

			if (rst) ddr_rst_r <= 1'b1; // enable DDR3 reset at system reset
			else if (fifo_re && (((waddr_fifo_out ^ SDRST_ACT_ADDR) & SDRST_ACT_ADDR_MASK)==0))
			ddr_rst_r <= waddr_fifo_out[0];

			if (rst) ddr_cke_r <= 1'b0;
			else if (fifo_re && (((waddr_fifo_out ^ CKE_EN_ADDR) & CKE_EN_ADDR_MASK)==0))
			ddr_cke_r <= waddr_fifo_out[0];

	if (rst) inv_clk_div_r <= 1'b0;		if (rst) inv_clk_div_r <= 1'b0;
	else if (fifo_re && (((waddr_fifo_out ^ EXTRA_ADDR) & EXTRA_ADDR_MASK)==0))		else if (fifo_re && (((waddr_fifo_out ^ EXTRA_ADDR) & EXTRA_ADDR_MASK)==0))
	inv_clk_div_r <= wdata_fifo_out[0];		inv_clk_div_r <= wdata_fifo_out[0];

ddrc_test01.v

+41 −14

Original line number	Original line	Diff line number	Diff line
	@@ -72,12 +72,15 @@ module ddrc_test01 #(
	parameter PAGES_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns		parameter PAGES_REL_MASK = 'h3ff, // address mask to set DQM and DQS patterns
	parameter CMDA_EN_REL = 'h022, // address to enable('h823)/disable('h822) command/address outputs		parameter CMDA_EN_REL = 'h022, // address to enable('h823)/disable('h822) command/address outputs
	parameter CMDA_EN_REL_MASK = 'h3fe, // address mask for command/address outputs		parameter CMDA_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
	parameter EXTRA_REL = 'h024, // address to set extra parameters (currently just inv_clk_div)		parameter SDRST_ACT_REL = 'h024, // address to activate('h825)/deactivate('h824) active-low reset signal to DDR3 memory
			parameter SDRST_ACT_REL_MASK = 'h3fe, // address mask for reset DDR3
			parameter CKE_EN_REL = 'h026, // address to enable('h827)/disable('h826) CKE signal to memory
			parameter CKE_EN_REL_MASK = 'h3fe, // address mask for command/address outputs
			parameter EXTRA_REL = 'h028, // address to set extra parameters (currently just inv_clk_div)
	parameter EXTRA_REL_MASK = 'h3ff // address mask for extra parameters		parameter EXTRA_REL_MASK = 'h3ff // address mask for extra parameters


	)(		)(
	// DDR3 interface		// DDR3 interface
			output SDRST, // DDR3 reset (active low)
	output SDCLK, // DDR3 clock differential output, positive		output SDCLK, // DDR3 clock differential output, positive
	output SDNCLK,// DDR3 clock differential output, negative		output SDNCLK,// DDR3 clock differential output, negative
	output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device		output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
	@@ -99,9 +102,7 @@ module ddrc_test01 #(
	);		);
	localparam ADDRESS_NUMBER=15;		localparam ADDRESS_NUMBER=15;
	// Source for reset and clock		// Source for reset and clock
	(* keep = "true" *)
	wire [3:0] fclk; // PL Clocks [3:0], output		wire [3:0] fclk; // PL Clocks [3:0], output
	(* keep = "true" *)
	wire [3:0] frst; // PL Clocks [3:0], output		wire [3:0] frst; // PL Clocks [3:0], output


	@@ -110,7 +111,7 @@ module ddrc_test01 #(
	(* keep = "true" *)		(* keep = "true" *)
	wire axi_aclk; // clock - should be buffered		wire axi_aclk; // clock - should be buffered
	// wire axi_aresetn; // reset, active low		// wire axi_aresetn; // reset, active low
	(* keep = "true" *)		(* dont_touch = "true" *)
	wire axi_rst; // reset, active high		wire axi_rst; // reset, active high
	// AXI Write Address		// AXI Write Address
	wire [31:0] axi_awaddr; // AWADDR[31:0], input		wire [31:0] axi_awaddr; // AWADDR[31:0], input
	@@ -209,7 +210,10 @@ module ddrc_test01 #(
	wire [ 1:0] port1_int_page;// input[1:0]		wire [ 1:0] port1_int_page;// input[1:0]

	// additional control signals		// additional control signals
	wire cmda_tri; // input		wire cmda_en; // enable DDR3 memory control and addreee outputs
			wire ddr_rst; // generate DDR3 memory reset (active hight)
			wire ddr_cke; // control of the DDR3 memory CKE signal

	wire inv_clk_div; // input		wire inv_clk_div; // input
	wire [ 7:0] dqs_pattern; // input[7:0] 8'h55		wire [ 7:0] dqs_pattern; // input[7:0] 8'h55
	wire [ 7:0] dqm_pattern; // input[7:0] 8'h00		wire [ 7:0] dqm_pattern; // input[7:0] 8'h00
	@@ -236,13 +240,26 @@ module ddrc_test01 #(

	always @ (posedge axi_rst or posedge axi_aclk) begin		always @ (posedge axi_rst or posedge axi_aclk) begin
	if (axi_rst) select_port0 <= 1'b0;		if (axi_rst) select_port0 <= 1'b0;
	else if (axird_start_burst) select_port0 <= (((axird_pre_araddr[11:10]^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);		else if (axird_start_burst) select_port0 <= (((axird_pre_araddr^ PORT0_RD_ADDR) & PORT0_RD_ADDR_MASK)==0);
	if (axi_rst) select_status <= 1'b0;		if (axi_rst) select_status <= 1'b0;
	else if (axird_start_burst) select_status <= (((axird_pre_araddr[11:10]^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);		else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
	end		end
			/*
	// Clock and reset from PS		// Clock and reset from PS
	BUFG bufg_axi_rst_i (.O(axi_rst),.I(~frst[0]));		reg frst_inv;
			always @ (negedge frst[0] or posedge axi_aclk) begin
			if (!frst[0]) frst_inv <= 1'b1;
			else frst_inv <= 1'b0;
			end
			*/
			`ifndef IVERILOG
			(* dont_touch = "true" *)
			`endif
			wire frst_inv= ~frst[0];


			//BUFG bufg_axi_rst_i (.O(axi_rst),.I(~frst[0]));
			BUFG bufg_axi_rst_i (.O(axi_rst),.I(frst_inv));
	BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));		BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));

	axibram_write #(		axibram_write #(
	@@ -325,6 +342,10 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
	.PAGES_REL_MASK (PAGES_REL_MASK),		.PAGES_REL_MASK (PAGES_REL_MASK),
	.CMDA_EN_REL (CMDA_EN_REL),		.CMDA_EN_REL (CMDA_EN_REL),
	.CMDA_EN_REL_MASK (CMDA_EN_REL_MASK),		.CMDA_EN_REL_MASK (CMDA_EN_REL_MASK),
			.SDRST_ACT_REL (SDRST_ACT_REL),
			.SDRST_ACT_REL_MASK(SDRST_ACT_REL_MASK),
			.CKE_EN_REL (CKE_EN_REL),
			.CKE_EN_REL_MASK (CKE_EN_REL_MASK),
	.EXTRA_REL (EXTRA_REL),		.EXTRA_REL (EXTRA_REL),
	.EXTRA_REL_MASK (EXTRA_REL_MASK)		.EXTRA_REL_MASK (EXTRA_REL_MASK)
	) ddrc_control_i (		) ddrc_control_i (
	@@ -344,7 +365,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
	.dly_addr (dly_addr[6:0]), // output[6:0]		.dly_addr (dly_addr[6:0]), // output[6:0]
	.ld_delay (ld_delay), // output		.ld_delay (ld_delay), // output
	.dly_set (set), // output		.dly_set (set), // output
	.cmda_tri (cmda_tri), // output		.cmda_en (cmda_en), // output
			.ddr_rst (ddr_rst), // output
			.ddr_cke (ddr_cke), // output
	.inv_clk_div (inv_clk_div), // output		.inv_clk_div (inv_clk_div), // output
	.dqs_pattern (dqs_pattern[7:0]), // output[7:0]		.dqs_pattern (dqs_pattern[7:0]), // output[7:0]
	.dqm_pattern (dqm_pattern[7:0]), // output[7:0]		.dqm_pattern (dqm_pattern[7:0]), // output[7:0]
	@@ -406,6 +429,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
	.CMD_PAUSE_BITS (CMD_PAUSE_BITS),		.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
	.CMD_DONE_BIT (CMD_DONE_BIT)		.CMD_DONE_BIT (CMD_DONE_BIT)
	) ddrc_sequencer_i (		) ddrc_sequencer_i (
			.SDRST (SDRST), // output
	.SDCLK (SDCLK), // output		.SDCLK (SDCLK), // output
	.SDNCLK (SDNCLK), // output		.SDNCLK (SDNCLK), // output
	.SDA (SDA[14:0]), // output[14:0] // BUG with localparam - fixed		.SDA (SDA[14:0]), // output[14:0] // BUG with localparam - fixed
	@@ -437,7 +461,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));

	.run_addr (run_addr[10:0]), // input[10:0]		.run_addr (run_addr[10:0]), // input[10:0]
	.run_chn (run_chn[3:0]), // input[3:0]		.run_chn (run_chn[3:0]), // input[3:0]
	.run_seq (run_seq), // input		.run_seq (run_seq), // input #################### DISABLED ####################
			// .run_seq (1'b0 && run_seq), // input #################### DISABLED ####################
	// .run_done (run_done), // output		// .run_done (run_done), // output
	.run_done (), // output		.run_done (), // output
	.run_busy (run_busy), // output		.run_busy (run_busy), // output
	@@ -462,7 +487,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
	.port1_int_page (port1_int_page[1:0]), // input[1:0]		.port1_int_page (port1_int_page[1:0]), // input[1:0]
	.port1_addr (axiwr_bram_waddr[7:0]), // input[7:0]		.port1_addr (axiwr_bram_waddr[7:0]), // input[7:0]
	.port1_data (axiwr_bram_wdata[31:0]), // input[31:0]		.port1_data (axiwr_bram_wdata[31:0]), // input[31:0]
	.cmda_tri (cmda_tri), // input		.cmda_en (cmda_en), // input
			.ddr_rst (ddr_rst), // input
			.ddr_cke (ddr_cke), // input
	.inv_clk_div (inv_clk_div), // input		.inv_clk_div (inv_clk_div), // input
	.dqs_pattern (dqs_pattern), // input[7:0]		.dqs_pattern (dqs_pattern), // input[7:0]
	.dqm_pattern (dqm_pattern) // input[7:0]		.dqm_pattern (dqm_pattern) // input[7:0]

ddrc_test01.xdc

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -19,6 +19,10 @@
	# along with this program. If not, see <http://www.gnu.org/licenses/> .		# along with this program. If not, see <http://www.gnu.org/licenses/> .
	#################################################################################		#################################################################################

			# output SDRST, // output SDRST, active low
			set_property IOSTANDARD SSTL15 [get_ports {SDRST}]
			set_property PACKAGE_PIN J4 [get_ports {SDRST}]

	# output SDCLK, // DDR3 clock differential output, positive		# output SDCLK, // DDR3 clock differential output, positive
	set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDCLK}]		set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDCLK}]
	set_property PACKAGE_PIN K3 [get_ports {SDCLK}]		set_property PACKAGE_PIN K3 [get_ports {SDCLK}]

ddrc_test01_testbench.sav

+225 −23

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