Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
D
doxverilog
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
doxverilog
Commits
98a9b24c
Commit
98a9b24c
authored
Aug 30, 2014
by
Dimitri van Heesch
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Bug 735623 - Expression is always false because 'else if' condition matches previous condition
parent
ff7cc1c7
Changes
2
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
2 additions
and
2 deletions
+2
-2
translator_ru.h
src/translator_ru.h
+1
-1
translator_ua.h
src/translator_ua.h
+1
-1
No files found.
src/translator_ru.h
View file @
98a9b24c
...
...
@@ -1605,7 +1605,7 @@ class TranslatorRussian : public Translator
}
else
{
if
(
isTemplate
)
result
+=
" Шаблон "
;
result
+=
" Шаблон "
;
switch
(
compType
)
{
case
ClassDef
:
:
Class
:
result
+=
"модуля"
;
break
;
...
...
src/translator_ua.h
View file @
98a9b24c
...
...
@@ -1596,7 +1596,7 @@ class TranslatorUkrainian : public TranslatorAdapter_1_8_4
}
else
{
if
(
isTemplate
)
result
+=
" Шаблон "
;
result
+=
" Шаблон "
;
switch
(
compType
)
{
case
ClassDef
:
:
Class
:
result
+=
"модуля"
;
break
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment