Commit 90d84927 authored by mk's avatar mk

adding document generate blocks

parent 94b6b6f2
...@@ -241,8 +241,8 @@ QCString VerilogDocGen::convertTypeToString(int type,bool sing) ...@@ -241,8 +241,8 @@ QCString VerilogDocGen::convertTypeToString(int type,bool sing)
if(sing) if(sing)
return "Miscellaneous"; return "Miscellaneous";
return "Miscellaneous"; return "Miscellaneous";
case(VerilogDocGen::GENERATE):
return "GENERATE";
default: return ""; default: return "";
} }
...@@ -377,6 +377,10 @@ void VerilogDocGen::writeVerilogDeclarations(MemberList* ml,OutputList& ol,Group ...@@ -377,6 +377,10 @@ void VerilogDocGen::writeVerilogDeclarations(MemberList* ml,OutputList& ol,Group
VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::PARAMETER,FALSE),0,FALSE,VerilogDocGen::PARAMETER); VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::PARAMETER,FALSE),0,FALSE,VerilogDocGen::PARAMETER);
VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::MODULE,FALSE),0,FALSE,VerilogDocGen::MODULE); VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::MODULE,FALSE),0,FALSE,VerilogDocGen::MODULE);
VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::GENERATE,FALSE),0,FALSE,VerilogDocGen::GENERATE
);
VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::CONFIGURATION,FALSE),0,FALSE,VerilogDocGen::CONFIGURATION); VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::CONFIGURATION,FALSE),0,FALSE,VerilogDocGen::CONFIGURATION);
VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::PORT,FALSE),0,FALSE,VerilogDocGen::PORT); VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::PORT,FALSE),0,FALSE,VerilogDocGen::PORT);
VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::FEATURE,FALSE),0,FALSE,VerilogDocGen::FEATURE); VerilogDocGen::writeVerilogDeclarations(ml,ol,cd,0,fd,gd,VerilogDocGen::convertTypeToString(VerilogDocGen::FEATURE,FALSE),0,FALSE,VerilogDocGen::FEATURE);
...@@ -586,6 +590,7 @@ void VerilogDocGen::writeVerilogDeclarations(MemberDef* mdef,OutputList &ol, ...@@ -586,6 +590,7 @@ void VerilogDocGen::writeVerilogDeclarations(MemberDef* mdef,OutputList &ol,
case VerilogDocGen::OUTPUT: case VerilogDocGen::OUTPUT:
case VerilogDocGen::INOUT: case VerilogDocGen::INOUT:
case VerilogDocGen::PARAMETER: case VerilogDocGen::PARAMETER:
case VerilogDocGen::GENERATE:
writeLink(mdef,ol); writeLink(mdef,ol);
ol.docify(" "); ol.docify(" ");
ol.insertMemberAlign(); ol.insertMemberAlign();
......
...@@ -90,7 +90,7 @@ static void parseParam(Entry* e); ...@@ -90,7 +90,7 @@ static void parseParam(Entry* e);
static void parseListOfPorts(); static void parseListOfPorts();
static void parseAlways(const char * s=0,bool b=false); static void parseAlways(const char * s=0,bool b=false);
static void parseModuleInst(QCString& first,QCString& sec); static void parseModuleInst(QCString& first,QCString& sec);
static void parseGenerate();
bool findExtendsComponent(QList<BaseInfo> *extend,QCString& compName); bool findExtendsComponent(QList<BaseInfo> *extend,QCString& compName);
void addSubEntry(Entry* root, Entry* e); void addSubEntry(Entry* root, Entry* e);
...@@ -991,7 +991,7 @@ named_port_connection : attribute_instance named_parameter_assignment ...@@ -991,7 +991,7 @@ named_port_connection : attribute_instance named_parameter_assignment
//----------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------
//generated_instantiation ::= generate { generate_item } endgenerate //generated_instantiation ::= generate { generate_item } endgenerate
generated_instantiation : GENERATE_TOK {CurrState=VerilogDocGen::STATE_GENERATE;generateItem=true;} generate_item_list ENDGENERATE_TOK {CurrState=0;generateItem=false;} generated_instantiation : GENERATE_TOK {CurrState=VerilogDocGen::STATE_GENERATE;generateItem=true;parseGenerate();} generate_item_list ENDGENERATE_TOK {CurrState=0;generateItem=false;}
| GENERATE_TOK error ENDGENERATE_TOK {CurrState=0;generateItem=false;} | GENERATE_TOK error ENDGENERATE_TOK {CurrState=0;generateItem=false;}
; ;
...@@ -2121,6 +2121,17 @@ if(currentVerilog) ...@@ -2121,6 +2121,17 @@ if(currentVerilog)
} }
} }
void parseGenerate(){
if(parseCode) return;
QCString name("GENERATE ");
QCString tmp;
tmp=tmp.setNum(getVerilogPrevLine());
name+="["+tmp+"]";
Entry* pTemp=VerilogDocGen::makeNewEntry(name.data(),Entry::VARIABLE_SEC,VerilogDocGen::GENERATE,getVerilogPrevLine());
}
void parseListOfPorts() { void parseListOfPorts() {
...@@ -2569,7 +2580,7 @@ void c_error(const char * err){ ...@@ -2569,7 +2580,7 @@ void c_error(const char * err){
if(err){// && !parseCode){ if(err){// && !parseCode){
//fprintf(stderr,"\n\nerror at line [%d]... : in file [%s]\n\n",c_lloc.first_line,getVerilogParsingFile()); //fprintf(stderr,"\n\nerror at line [%d]... : in file [%s]\n\n",c_lloc.first_line,getVerilogParsingFile());
vbufreset(); vbufreset();
// exit(0); //exit(0);
} }
} }
......
...@@ -1337,7 +1337,7 @@ GATETYPE "and"|"nand"|"or"|"nor"|"xor"|"xnor"|"buf"|"bufif0"|"bufif1"|"not"|"n ...@@ -1337,7 +1337,7 @@ GATETYPE "and"|"nand"|"or"|"nor"|"xor"|"xnor"|"buf"|"bufif0"|"bufif1"|"not"|"n
<Start>"end" { if(check()) { yyEndLine=yyLineNr; strncpy(c_lval.cstr,verilogscannerYYtext,verilogscannerYYleng);c_lval.cstr[verilogscannerYYleng]='\0';return END_TOK;}REJECT;} <Start>"end" { if(check()) { yyEndLine=yyLineNr; strncpy(c_lval.cstr,verilogscannerYYtext,verilogscannerYYleng);c_lval.cstr[verilogscannerYYleng]='\0';return END_TOK;}REJECT;}
<Start>"begin" {if(check(false)) return BEGIN_TOK; REJECT;} <Start>"begin" {if(check(false)) return BEGIN_TOK; REJECT;}
<Start>"fork" {if(check(false)) return FORK_TOK; REJECT;} <Start>"fork" {if(check(false)) return FORK_TOK; REJECT;}
<Start>"generate" { if(check()) return GENERATE_TOK;REJECT;} <Start>"generate" { if(check()) {yyPrevLine=yyLineNr; return GENERATE_TOK; }REJECT;}
<Start>"endgenerate" { if(check()) return ENDGENERATE_TOK;REJECT;} <Start>"endgenerate" { if(check()) return ENDGENERATE_TOK;REJECT;}
<Start>"genvar" { if(check()) return GENVAR_TOK;REJECT;} <Start>"genvar" { if(check()) return GENVAR_TOK;REJECT;}
<Start>"default" { if(check()) return DEFAULT_TOK;REJECT;} <Start>"default" { if(check()) return DEFAULT_TOK;REJECT;}
......
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